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fel88

SERDES doesn't work as expected

Question

Hi, my board is Zybo-Z7 20

I am trying to run simple scheme with 2 serdes blocks.

I have got 2 switches and 2 leds. 

I want to run next scheme:

2 switches -> Serializer (2:1) -> ...... TMDS ....... -> Deserializer (1:2)  -> 2 leds

 

I've connected PMOD JB1 -> JB2 with 2 wires.

But I can't restore a valid signal.

I recieve only 11 or 00. (00->00, 01->11, 10->11, 11->11)

 

Serializator settings:

1618932420_.png.467482a47a276f3c7bd412450ec8f949.png

Deserializator settings:

1495991564_.png.0f5741e3eb8dd5637f815bfd1c7397b3.png

 

Scheme:

336934443_.thumb.png.51acf8e8d4c5ec968846d7b2e272fa57.png

 

clk_10 =10 MHz

clk_20 = 20 Mhz

 

Zybo-Z7-Master.xdc

209416878_.png.ceba4b1cca847a02e2b64f6017de6d7d.png

 

Top.v:

  design_1 d0 (    
      .sw0(sw0),
       .sw1(sw1),
       .lvds_in_p(jb_in_p[0]),
       .lvds_in_n(jb_in_n[0]),
       .lvds_out_p(jb_out_p[0]),
      .lvds_out_n(jb_out_n[0]),
      .sysclk(sysclk),    
      .led2(led2),
      .led3(led3)
   );

I/O:

965142102_.thumb.png.85bac2d198abc0ca0c56a569efd70dd7.png

 

What is wrong ? Should I use some resistors on TMDS line?

 

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57 minutes ago, fel88 said:

I've tried to add 50Ohm resistor between lines.

If you want to have any success in FPGA design space, you will need to love reading. In this case, UG471 has everything you need to know.

Specifically, it says this:

Quote

TMDS (Transition Minimized Differential Signaling)
TMDS is a differential I/O standard for transmitting high-speed serial data used by the DVI and HDMI video interfaces. The TMDS standard requires external 50Ω pull-up resistors to 3.3V on the inputs. TMDS inputs do not require differential input termination resistors. TMDS is only available in HR I/O banks and requires a VCCO voltage level of 3.3V. The IOSTANDARD is called TMDS_33. Table 1-52 summarizes all the possible TMDS I/O standards.

TMDS belongs to the family of physical standards which are driven by the current as opposed to voltage level as previous ones did. This has a number of important advantages for high-speed communications, but it also requires a complete circuit to actually see the data. Different standards approach this in a different way - some require termination to Vcc, some - to ground, yet some - to a midpoint or some other reference level. TMDS uses termination to the Vcc. So you need to have external termination of ~50 Ohm to VCCIO rail of 3.3 V in order for your loopback to work.

Edited by asmi

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23 minutes ago, fel88 said:

Should I use some resistors on TMDS line?

If you are using TMDS33 then you MUST have 50 ohm termination. See the Series7 Select IO user guide.

I'm not sure what exactly you are trying to do here but you'd be far better off using an HDL rather than the board design flow. Trying to use really slow clocks out of an MMCM and switch inputs for output data and LEDs for input data is not a very effective way to explore this. 

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I've also tried 60/120 MHz clocks. 

I've tried to add 50Ohm resistor between lines.

I've tried to set pull-up like this:

set_property -dict {PACKAGE_PIN V8 IOSTANDARD TMDS_33 PULLUP true} [get_ports {jb_out_p[0]}]
set_property -dict {PACKAGE_PIN W8 IOSTANDARD TMDS_33 PULLUP true} [get_ports {jb_out_n[0]}]

Unfortunately, all my attempts didn't bring any meaningful results.

Maybe someone could provide a working SERDES loopback project?

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2 minutes ago, fel88 said:

I've tried to add 50Ohm resistor between lines.

That's not how TMDS termination works. Read the material that I've suggested. Do not try and connect custom hardware or wires to your board unless you understand supported IOSTANDARD specifications and terminations for your device and bank Vccio. TMDS_33 termination resistors are external. The FPGA IO PULL_UP and PULL_DOWN are not suitable. Again, you need to do your homework before starting any experimentation.

You are not likely to find what you are looking for using Xilinx IP. and the board design flow. You will have better fortunes if you learn Verilog or VHDL. The Digilent staff are keen on the board design approach perhaps you will be lucky and one of them will have some suggestions. But really, the appropriate thing to do here is write your own HDL to experiment with IOSERDES.

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One thing I remember when using SERDES is that they require a proper reset procedure before they are functional. So try adding a reset block (you can use "Processor Reset Block" to sync incoming async reset to the system frequency if you don't feel like doing so HDL) and connecting it to a reset inputs of your SERDES blocks.

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Looking at the static levels of digital signals is analogous to looking at a picture of the front of an elephant and trying to peek around to see its rear. You can't because a picture is just a 2D representation of a 3D object. Trying to look at the static state of a signal is similar. You need to have another dimension which is time. For something like SERDES where there are multiple transitions per clock just make things more complicated. I'm glad that you got to your initial goal. I'm hoping that you don't stop there but can take more steps.

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