How to generate a higher frequency than input frequency using DDS compiler from xilinx

[jean]

Hi , I am using DDS compiler to generate sin and cos  I know that  the DDS iP cannot generate an output frequency higher than the input frequency(clock system). I am very grateful if any person can give me any idea to generate a higher frequency than the input. I need to have an output more than 2.6 GHz. Thanks a lot for any idea. I am grateful a lot.  persons speak about polyphased DDS but I am not able to undestand how can I do this implementation to have a higher frequency than the input. Thanks a lot

[zygot]

I did manage to bump into pg269-rf-data-converter.pdf. While not as expansive as I'd want it does shed some light on how the DDC and DUC work using the hardware NCO and mixer components. I suspect that for now at least you are stuck with using Xilinx IP if you want to use the converters. You might want to read this IP user guide.

[edit] I believe that you need to use Xilinx IP but be aware that you have to use specific hardware paths between your baseband logic and the converters. The normal DDC and DUC IP for other devices that I'm familiar with aren't appropriate. Have you tried getting help on the Xilinx User Community website? It's a real pain to use and often not helpful for specific issues but Digilent neither sells nor supports products based on your device and most users of the Digilent Forums have no experience with it.

[zygot]

21 minutes ago, D@n said:

The MPSOC manual I have suggests support for 100GHz outputs

I'm not sure what you are looking at or what "suggests support for" means. I'm pretty sure that you can't afford to buy any high end FPGA devices. There have been companies that have implemented very high speed FPGA architectures using exotic materials supporting GHz level logic clocking but I'm not sure that any have survived. If they have then they have a very small customer base with lots of money to spend.

Here's an alternate quickie analysis.

I recently posted about a project that I did in fact implement in an Artix XEM7320 to capture 4 channels of 100 MHz ADC samples into 4 128 M sample buffers. The DDR memory is 32 bit wide and runs at 400 MHz. That's 64 bits of data per clock or an aggregate of 25.6 Gbps peak data rate. Let's say that you have 16-bit sine and cosine data samples for a 32-bit sample word. That works out to less than 1 G sample/s. This is done with the help of the Xilinx MIG external memory IP and carefully laid out PCB traces using IO banks specifically supporting DDR memory. Perhaps you can find an expensive board with a Virtex part supporting DDR 1600 speeds. You still aren't close to the 83.2 Gbps aggregate data rate you need. Then there's the problem of supporting the interface of whatever you expect to connect your DDS data to as well as finding the IO to do it. At a minimum you are talking about a custom FPGA board.. Lastly you have to figure out how to create and mux all of those DDS cores to fabricate one useful signal.

Many years ago I worked on a similar project. We used the AD9957 which makes the whole problem much simpler. All you have to do is feed it I/Q data and it does the up conversion. That device support 1 GHz signals.

 

[zygot]

35 minutes ago, jean said:

Hi I am using ZCU111 board

Well... that does make a difference.

To feed the DDR controller that I mentioned earlier I used a 1024-bit data bus to work with the controller low speed clock rate. The width conversion was done by the BRAM in an asymmetric FIFO. I would expect problems trying to do it in logic.

II certainly wouldn't want to try this using multiple instances of the Xilinx DDS IP.  I might be wrong but I suspect that Vivado HLS is not a viable way to go, but I have no experience with Xilinx support for the RFSOC devices.

[jean]

15 hours ago, D@n said:

@jean,

Help me out here, what is "the IP DDC DUC from xilinx"?  and ... Why is it that it cannot help you?

Dan

Hi, this IP presents  the Digital Up Converter (DUC) and Digital Down Converter (DDC),  as mentioned in the datsheet,  The Xilinx LogiCORE™ IP DUC/DDC Compiler generates Digital Up-Converter modules for a range of output sample rates between 30.76 and 245.76 MHz. These frequencies are far below the desired frequencies 

[D@n]

@jean,

The answer to this question really depends upon your application.  What kind of waveform will you be sending?  What is its bandwidth?  Do you just intend to transmit a narrowband tone?  A carefully crafted pulse?  A narrowband (<100MHz) communications signal?  Or an ultra-wideband signal?  Each application needs a different answer, and has a different associated cost.

Dan

[jean]

18 minutes ago, D@n said:

@jean,

The answer to this question really depends upon your application.  What kind of waveform will you be sending?  What is its bandwidth?  Do you just intend to transmit a narrowband tone?  A carefully crafted pulse?  A narrowband (<100MHz) communications signal?  Or an ultra-wideband signal?  Each application needs a different answer, and has a different associated cost.

Dan

Hi, my application is the LTE 4G, the bandwidth is 20 MHz, I am thinking about generating sine and wave(IQ data) at 30.72 MHz then using the IP DUC then the DAC but I am not sure it was be correct or not(for an LTE system at 20 MHz channel bandwidth, the input of this IP correspond to 30.72 MSPS and the output which correpsond to the RF sample rate is ranging to 245,76 MSPS. Using DDS compiler at 30.72 MHz for IQ data then DUP then DAC to have the desired output

[D@n]

@jean,

That might make the task *much* easier.  Consider (instead) building your signal of interest at 50MHz (or so), and then multiplying by a sine wave whose wavelength is an integer multiple of your oversample factor.  For example, if you are oversampling by 32:1, multiply by a sine wave with four periods per every sample.  That'll get you up to speed.  Smaller frequency offsets can be handled in your original 50Msps domain if necessary.

This operation will also introduce some aliasing products, just not from the sinwave.  Whether or not those aliasing products are material to your application or not is another question. 

The alternative would be to first upsample, then multiply by the sinewave.  Building a linear upsampler isn't that hard.  Neither is a quadratic.  Beware, though, that any upsampler you build will have an impact on the passband of your signal.  Something to think about.

I should also point out ... up and downsamplers aren't that hard to build.  Limiting yourself to Xilinx's tools would be .... well, limiting yourself.

Dan

[zygot]

I hadn't realized that Xilinx started delivering evaluation boards for its RFSOC devices. I did try and get available datasheets for your device and I think that I understand the nature of your confusion now. If Xilinx has published the information relevant to your questions then I wasn't able to find it.

Fmax for the the PL global clock buffer is 775 MHz. This is also the maximum MMCM output clock rate. For comparison Fmax for the global clock buffer is 710 MHz for the Kintex on my Genesys2 and the maximum MMCM output is 933 MHz. This would suggest an upper baseband clock rate.  The PLL is a bit more interesting. The datasheet lists PL_Foutmax as 667-775 MHz for the clkouts but also 2133-2667 for clkoutphy. I haven't been able to find published information about the devices PL resources yet. My guess is that the clkoutphy is used to drive the DDC and DUC elements, which I'm guessing are hardware based.

I ca only offer conjecture about how the converters connect to baseband signals because I don't have the pertinent information. I would hope that customers who've purchased kits would have access to this information.

[zygot]

21 minutes ago, D@n said:

I should also point out ... up and downsamplers aren't that hard to build.  Limiting yourself to Xilinx's tools would be .... well, limiting yourself.

I totally agree with the second sentence if it stood by itself but in the context of this thread and the with the preceding sentence I'm intrigued. Please elaborate.

[jean]

29 minutes ago, zygot said:

I hadn't realized that Xilinx started delivering evaluation boards for its RFSOC devices. I did try and get available datasheets for your device and I think that I understand the nature of your confusion now. If Xilinx has published the information relevant to your questions then I wasn't able to find it.

Fmax for the the PL global clock buffer is 775 MHz. This is also the maximum MMCM output clock rate. For comparison Fmax for the global clock buffer is 710 MHz for the Kintex on my Genesys2 and the maximum MMCM output is 933 MHz. This would suggest an upper baseband clock rate.  The PLL is a bit more interesting. The datasheet lists PL_Foutmax as 667-775 MHz for the clkouts but also 2133-2667 for clkoutphy. I haven't been able to find published information about the devices PL resources yet. My guess is that the clkoutphy is used to drive the DDC and DUC elements, which I'm guessing are hardware based.

I ca only offer conjecture about how the converters connect to baseband signals because I don't have the pertinent information. I would hope that customers who've purchased kits would have access to this information.

 

32 minutes ago, D@n said:

@jean,

That might make the task *much* easier.  Consider (instead) building your signal of interest at 50MHz (or so), and then multiplying by a sine wave whose wavelength is an integer multiple of your oversample factor.  For example, if you are oversampling by 32:1, multiply by a sine wave with four periods per every sample.  That'll get you up to speed.  Smaller frequency offsets can be handled in your original 50Msps domain if necessary.

This operation will also introduce some aliasing products, just not from the sinwave.  Whether or not those aliasing products are material to your application or not is another question. 

The alternative would be to first upsample, then multiply by the sinewave.  Building a linear upsampler isn't that hard.  Neither is a quadratic.  Beware, though, that any upsampler you build will have an impact on the passband of your signal.  Something to think about.

I should also point out ... up and downsamplers aren't that hard to build.  Limiting yourself to Xilinx's tools would be .... well, limiting yourself.

Dan

Thanks for your explication, you suggest me as a start, i try to limit myself on xilinix IPs ie use IP DDS + IP DUC digital up converter to see these limits. generating a sine + cos using using DDS at 30.72 MHz then connceting its to DUC, I see the result then connect them to DAC and see the reuslts? 

[jean]

13 minutes ago, zygot said:

I totally agree with the second sentence if it stood by itself but in the context of this thread and the with the preceding sentence I'm intrigued. Please elaborate.

I dont know if I limited for the moment to generate a sin+cos wive runing at 30.72 MHz( base band sample rate of IP DUC is 30.72 MSPS), using this you can have an output until 245.74 MSPS(RF sample rate) then connect its to the DAC  with trying to properly configure the DAC. Sorry for my many question, this is my first project that I will do.

[D@n]

@jean,

Let's start with the DAC then.  What's the maximum sample rate, based upon its data sheet, that it can produce?  Second question would be, how many bits wide is it?  That should settle a lot of our questions.

Dan

[zygot]

9 minutes ago, jean said:

Sorry for my many question, this is my first project that I will do.

If this is your first FPGA project you jumped into the deep end of the pool. The UltraScale devices are a lot more complicated than the normal devices used in products normally discussed in the Digilent Forum and the key information tends to be a lot more difficult to tease out.

The first thing that you want to do is try to at least build the demo projects that come with your development kit. You might not be able to run them due to odd requirements. This is what I ran into with the ZCU106 TRD. But, with a bit modification of the tcl I did manage to build the demo.

[xc6lx45]

A sneaky way out of it is to use n (e.g. n=8 ) generators in parallel, with a phase offset of 1/n sample.  This is literally a "polyphase" approach.

For high-end fast DA / AD converters you won't be able to operate at the converter's clock rate on an FPGA so it needs to be split on multiple, parallel lanes anyway.

 

[jean]

31 minutes ago, xc6lx45 said:

A sneaky way out of it is to use n (e.g. n=8 ) generators in parallel, with a phase offset of 1/n sample.  This is literally a "polyphase" approach.

For high-end fast DA / AD converters you won't be able to operate at the converter's clock rate on an FPGA so it needs to be split on multiple, parallel lanes anyway.

 

Hi, please can you give me more detail this approch. How can I do it. thanks

[xc6lx45]

OK I just read the LTE part.

I suspect this is a RF systems design question, lacking the analog / RF upconverter (which is outside the FPGA).

30.72 MHz sample rate for LTE20 is standard at baseband. Upsampling by 8 to 245.76 MHz sounds meaningful as well (depends on the converters / filters that are available). What's missing is the step from there to RF, which might be either direct conversion (using the BB signal centered at 0 Hz) or something more complex (using a non-0 Hz DAC signal) which is easier from RF point-of-view e.g. thanks to the lower ("non-infinite") fractional bandwidth. Don't be fooled by the apparent simplicity of direct conversion - it's not if you know of all the correction algorithms no one ever mentions. DC makes sense if you intend to sell billions of units, not build a simple working prototype. Superhet is the ticket, usually, with a few suitable acoustic or cavity filters.

The question I'd ask is, "what is the intermediate frequency"? Knowing that, designing the digital upconversion is a routine job, possibly involving cascaded halfband filters if it's meant to be cheap.

The step from IF to RF e.g. 900 MHz or 2.5 GHz needs to be bridged with dedicated radio-frequency circuitry e.g. diode ring mixer unless you're really sure you've done your homework.

My "polyphase" answer addresses the first post but I suspect even a good answer to a bad question is equally useless.

[jean]

3 minutes ago, xc6lx45 said:

OK I just read the LTE part.

I suspect this is a RF systems design question, lacking the analog / RF upconverter (which is outside the FPGA).

30.72 MHz sample rate for LTE20 is standard at baseband. Upsampling by 8 to 245.76 MHz sounds meaningful as well (depends on the converters / filters that are available). What's missing is the step from there to RF, which might be either direct conversion (using the fundamental signal centered at 0 Hz) or something more complex (using a non-0 Hz DAC signal) which is easier from RF point-of-view e.g. thanks to the lower ("non-infinite") fractional bandwidth. Don't be fooled by the simplicity of direct conversion - it's not and makes sense if planning to sell billions of units, not build a simple working prototype. Superhet is the ticket, usually.

The question I'd ask is, "what is the intermediate frequency"? Knowing that, designing the digital upconversion is a routine job, possibly involving cascaded halfband filters if it's meant to be cheap.

The step from IF to RF e.g. 900 MHz or 2.5 GHz needs to be bridged with dedicated radio-frequency circuitry e.g. diode ring mixer unless you're really sure you've done your homework.

My "polyphase" answer addresses the first post but I suspect even a good answer to a bad question is equally useless.

The ZCU111 contains a DAC allowing its to convert directiy to RF, I am thinking to generating a sin cos using DDS compiler running at 30.72 MHz then connecting its to DUP CONVERTER to have the 245.76 MHz then to the IP DAC with interpolation of the DAC; I can reach to result. what do you think? 

[zygot]

@xc6lx45,

Spoiler Alert! This is one of those ZYNQ beasts with onboard ADC and DAC converters. The issue is essentially a lack of documentation and transparency on the part of Xilinx on how their devices work.  My earlier posts to this thread shows that I didn't get it at first either.

[xc6lx45]

I think the first thing I'd check is the jitter performance of the available DAC clock (its impact is proportional to the highest frequency component you're generating). The second thing I'd check is 14 bit (or whatever Nyqust equivalent performance they promise) against the LTE uplink specs. See TS 36.101. I don't think it will fly but I haven't done my homework (nor do I have the input what you're actually trying to achieve e.g. in terms of specs compliance). Check unwanted emissions, not so much close in to your signal (where the requirements are quite forgiving) but far away "out-of-band".

Note, I've quoted the handset ("user equipment" UE) specs. Basestations ("eNB"), that's another beast still...

[zygot]

On 9/15/2020 at 2:24 PM, D@n said:

The MPSOC manual I have suggests support for 100GHz outputs.  While this seems far fetched for me, I haven't dug into the statement to see either how they are managing it or how to set up that speed under the hood.  If 100GHz is doable, surely 2.6GHz is as well. 

@D@n, I just got an email from a well known high end FPGA board vendor claiming 200 Gbps Digital IO. Yes this is far fetched but I had to know why a respected vendor would make such a claim. The answer turns out to be OCuLink. No, I was unaware that this is a thing but a google search returns plenty of hits. Some variants of the RfSoC have multiple lanes of transceivers that run at 25 Gbps. Connect 8 of these transceivers to an interface and you have 200 Gbps of something. Calling that something digital IO is beyond misleading. PCIe transceivers aren't like Select IO pins. My PCs have spare 4 lane Gen 3 (8 Gbps) slots. What do you think my chances of using one for GPIO are?

BTW, finding OCuLink hits for things that you can connect to your 200 Gbps FPGA board interface is a different proposition. Beware of marketing claims. They can take a kernel of truth and turn it into a fantastical claim... unless you understand the context. The FPGA vendor claims that it can use this interface to connect two boards with a very high speed interface. Now that's believable but practical sustained data rates would likely be no where near 25 GB/s.

[edit] It's curious that these beasts have such limited PL logic clocking support given the capability of the PS hard logic and the transceivers.

[jean]

Please @D@n @xc6lx45  have any idea how can I solve this problem. 

[jean]

Hi,  I am using DDS compiler to generate sin and cos( IQ data) running at 30.72 MHz. I have choosing clock frequency= the input freqeuncy of the DDS= 245.76 MHz, phase width=10 bits, output width=16 bits, phase data=128. When I implement only the DDS and I simulate it, I have no problem. I can see sin and cos wave running at 30.72 MHz(period= 32.56 ns). Please see this figure. 

In this step, I have no problems, I can generate IQ data running at 30.72 MHz, but when I connect the DDS compiler to Digital Up Converter(wirelless standar LTE=20 MHz, base band sample rate= 30.72 MHz, RF sample rate=245.76 Msps, clock frequency= 245.76 MHz. The frequency of the generated IQ data from DDS compiler are changed(period=260 ns) the frequency are changed, I dont know and the generated sin and cos from duc_ddc_compiler are not equivalent to the frequency 245.76 MHz. Plase see the test becnh. Please if any person can give me a solution. 

 

 

I dont know where is the incorrect point why the frequency of IQ data from DDS compiler are changed and why the output of duc dont correspond to 245.76 MHz. I am very grateful. 

[D@n]

@jean,

8 minutes ago, jean said:

I thinks that i dont undestand ...

This is the perfect place to start a journey.  Just be prepared to make a lot of mistakes along the way.  I've certainly enjoyed my own journey so far.

One of my FPGA mentors once told me: Pick a frequency, and build everything for that frequency.  I have chosen 100MHz on a Basys3 (series-7 Xilinx FPGA), and so everything I tend to build runs at that frequency.  This translates to (roughly) 80MHz on a Spartan 6, 50 MHz on an iCE40 HP*, 25MHz on an iCE40 LP*, and perhaps 140MHz+ on a Kintex.  With a little work, I can build a design for a Xilinx FPGA at 200MHz, but it'd be a *lot* of work to retool everything I've ever done for this speed--not that I haven't thought about it.  So, let's allow a 200MHz clock as a reasonable logic speed.

Using a 200MHz clock you can generate a sine wave internally at 100MHz.  If you want to go faster, you'll need to run multiple sine wave generators in parallel.  You will pay for this in terms of area on your FPGA, but it's often quite doable.  Theoretically, if you could bring a 2.6 GHz signal into an FPGA (you'd need to sample at 5.2GHz or more), you could process 32 samples at a time and so handle the issue.  You'll still have to deal with a nightmare I/O problem, but it's not beyond the realm of the possible.  It might just be a lot cheaper to build some analog up-front processing first ...

You should also know that Xilinx's DDS is not the only solution out there.  At this speed, you might want a basic table lookup instead for your sin/cos generation.  Phase processing is still pretty easy, so don't get attached to Xilinx's DDS for that--it's pretty easy to do on your own.

Dan

[D@n]

@jean,

Might depend upon how much quality you need in that 2.6GHz output, and how you intend to output it.  Most FPGA I/O's won't work at that speed.  Keeping multiple I/O's together, so as to drive a high quality A/D, might also be a challenge.  Just outputting a signal that toggles at that speed--not nearly as much of a challenge.

Dan

[jean]

Thanks a lot for your reponse. Please can you give me an idea to increase the frequency of the DDS . The DDS should generate sin and cos. I the amplitude of cos Q is the amplitude of sin. For example , as a start if I want to have an 1GHz in output, How can I do, how can dds compiler, I think I should use many dds but I dont undestand how. or maybee I should use DUC converter but I think that this IP is not able to have higher frequency more than 1 GHz. Thanks a lot sir. I am very grateful if you help me