CMOD A7 - IO Clock Placer Failed

[stschmalz]

So I am student who has just started working with FPGA's and the CMOD A7-35T board.  I am trying to get my feet wet and implement a very basic design, however during implementation I get an error:

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
	< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_IBUF[1]] >

	btn_IBUF[1]_inst (IBUF.O) is locked to IOB_X0Y112
	 and btn_IBUF_BUFG[1]_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

 

The VHDL that I am using is as follows:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity blinky is
    Port ( led : out STD_LOGIC;
           btn : in STD_LOGIC_VECTOR(1 downto 0));
end blinky;

architecture Behavioral of blinky is
begin
    dff: process(btn)
    begin
        if (btn(1)='1') then
            led <= btn(0);
        end if;
    end process dff;
end Behavioral;

 

And my constraints file contains the following:

## LEDs
set_property -dict { PACKAGE_PIN A17   IOSTANDARD LVCMOS33 } [get_ports { led }]; #IO_L12N_T1_MRCC_16 Sch=led[1]

## Buttons
set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L19N_T3_VREF_16 Sch=btn[0]
set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L19P_T3_16 Sch=btn[1]

 

I am sure it is something very simple that I just do not understand yet so any help would be greatly appreciated.

Thanks!

[xc6lx45]

Hi,

for your toy example, you can safely enter

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn_IBUF[1]]

into the TCL command line and the warning should go away (this should cause no issues at low speed, say low MHz range)

Without going into details, you may find that the most "simple" examples will become very complex (in a sense of getting down to the bottom what is actually happening on the FPGA) because you're deviating from standard design patterns (synchronous logic) that has information moving from register to register on a clock edge (and that clock needs to be on a true clock pin for your error to go away, which is the case for the CMOD A7 if you use the 12 MHz built-in clock)