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Running Looper demo on Nexys Video board


Hi All,

First post on this forum.  Been trying to get the looper demo to work on the Nexys Video and encountering "mismatched array sizes in rhs and lhs of assignment" errors.  Please see details in attached screen shot.  Any pointers in the right direction would be much appreciated.

Best regards




Screenshot 2020-09-12 at 10.14.29 AM.png

Edited by specpro30
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Hi @specpro30,

I asked one of our content creators/maintainers about the Nexys Video Looper demo since it looks like the materials we have for it were only created for Vivado 2015.4 and 2016.4 and they let me know that "very low" was a reasonable way of describing for getting the Nexys Video Looper demo working on Vivado 2020.1. It may be possible to do, but we have not dedicated the resources in making this jump.

Thank you,

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Hi @JColvin

Thanks for getting back to me.  That’s a little disappointing as I bought the dev board for this purpose.  Perhaps I could try to set it up myself and share the results.  Where would I be able to find more info about the error mismatched array sizes in rhs and lhs of assignments?  It seems to be something to do with the OLED setup?

Many thanks!

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12 hours ago, specpro30 said:

That’s a little disappointing as I bought the dev board for this purpose.

Sometimes you have to work in non-ideal circumstances. I have numerous versions of Altera and Xilinx tools installed for precisely this reason. Fortunately, the size of Vivado 2015 isn't nearly as big a problem as current versions. As long as you aren't running two versions of the same tools simultaneously you can be productive. There are a number of good reasons to have multiple tool installations, but mostly this is to save the time of fixing broken IP. Of course, if you have the time to track down problems and solutions then that's a better approach. It's not uncommon for FPGA vendors to offer free IP and then take it away. Just one more reason to avoid vendor IP.

It's a shame that most FPGA board vendor support for their own boards is so limited and wed to design flows that constrain customer use of those products. This is especially disconcerting when the tools themselves stop supporting the IP that makes the products useful. Abandon the playpen. Stick to IP that you have the source code for when possible,

BTW. Some vendor IP provides readable source code. Some has a mix of readable and encrypted source. One more reason why older tool versions have some value.

I thought that a different perspective on your issue might be useful.

[edit] The latest version of FPGA vendor tools is not always the best, or even appropriate version to work with. It all depends on what you want to do, how much tie you have to do it, and what hardware you are using for physical  implementation.

Edited by zygot
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1 hour ago, specpro30 said:

Just to let everyone know that the demo works on 2019.

Thanks for the post. BTW, Xilinx made some basic changes to how it implements IP with Vivado 2019.2 ( a version which also forces a migration to Vitas for ZYNQ users ). It's the first time that Vivado has broken older all HDL projects relying on PLL, BRAM, FIFO, etc IP. It's possible to buy a new Xilinx development board that requires using the latest version of Vivado for device support but I have no reason to use anything beyond Vivado 2019.1 for any of my work. Why put up with a  constant barrage of nasty surprises if you don't need to?

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