Clock wizard simulation

[youngpark]

Hello,

I am trying to run simulation with design_wrapper(from IP block design including clocking wizard and two custom modules).

At clocking wizard, Input is sys_clock(MMCM, single ended, 12MHz, target board : cmod A7 35T) output clock frequency( setting : 40MHz) with no reset, no locked port.

When I run simulation with testbench, the sys_clock waveform was shown, but output clock doesn't show.

I think two things are weird.

first, clock_out1's frequency is to low. (The expected value should be at least 3 times faster than clk_in1)

second, clock_out came out just one cycle.

I read the clocking manual but couldn't find the reason.

Thank you in advance!

[JColvin]

Hi @youngpark,

I would recommend taking a look at these two Xilinx threads (link1, link2) which discuss a similar problem.

Thanks,
JColvin