[Common 17-69] Command failed: 'L16' is not a valid site or package pin name.

[vidar_silent_god_of_vengea]

I've attempted to perform implementation but I have received the following error, that appears associated with my xdc constraint file. Here are the errors I'm receiving:

• [Common 17-69] Command failed: 'L16' is not a valid site or package pin name.   Note: this goes for every pin value in the constraint block.
• [Vivado 12-1411] Cannot set LOC property of ports, Site location is not valid 

I've used the nxys4_constraints specified in the Nexys-4-DDR-Master.xdc, referenced https://github.com/Digilent/digilent-xdc/blob/master/Nexys-4-DDR-Master.xdc with the only code modification a being the reference of SEG7_CATH[n] as follows:

##Switches set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {SW[0]}] set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports {SW[1]}] set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {SW[2]}] set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports {SW[3]}] ##7 segment display set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {SEG7_CATH[0]}] set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports {SEG7_CATH[1]}] set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {SEG7_CATH[2]}] set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {SEG7_CATH[3]}] set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {SEG7_CATH[4]}] set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {SEG7_CATH[5]}] set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {SEG7_CATH[6]}] set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {SEG7_CATH[7]}] set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS33} [get_ports {AN[0]}] set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports {AN[1]}] set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {AN[2]}] set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports {AN[3]}] set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {AN[4]}] set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {AN[5]}] set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {AN[6]}] set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {AN[7]}]

Synthesis runs smoothly, but not Implementation. What am I doing wrong?

 

My VHDL is as follows:

---------------------------------------------------------------------------------
-- Description:
-- Tutorial Top Level which displays the SW(3:0) input as a hexidecimal digit
-- on one of the 7-SEGMENT displays
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity top_level is
    Port (
        SW : in STD_LOGIC_VECTOR (3 downto 0);
        SEG7_CATH : out STD_LOGIC_VECTOR (7 downto 0);
        AN : out STD_LOGIC_VECTOR (7 downto 0));
end top_level;

architecture Behavioral of top_level is

    signal display_digit : std_logic_vector(3 downto 0);
 
begin

    display_digit <= SW(3 downto 0);
 
    with display_digit select
        SEG7_CATH <=
         "11000000" when x"0" ,
         "11111001" when x"1" ,
         "10100100" when x"2" ,
         "10110000" when x"3" ,
         "10011001" when x"4" ,
         "10010010" when x"5" ,
         "10000010" when x"6" ,
         "11111000" when x"7" ,
         "10000000" when x"8" ,
         "10010000" when x"9" ,
         "10001000" when x"A" ,
         "10000011" when x"B" ,
         "11000110" when x"C" ,
         "10100001" when x"D" ,
         "10000110" when x"E" ,
         "10001110" when others;

    AN <= (0=>'0', others=>'1'); --Note: this only shows up on display 0
end Behavioral;
 

 

[JColvin]

Hi @vidar_silent_god_of_vengea,

Which Nexys board do you have? The original Nexys 4, the Nexys 4 DDR, or the Nexys A7?

Thanks,
JColvin