DDS compiler + IFFT in vivado HLX

[jean]

Hi, I present my self, I am new a new engineer in FPGA. This is the first time that I use FPGA after university.  I am using DDS compiler V6.0 in order to generate cos and sin which represents the I and Q data. I is the amplitude of cos and Q represents the amplitude of sin. The objective is to compute the IFFT of these generated IQ data using the IFFT core of Xilinx. Please have any idea how configure the DDS compiler and IFFT in order to correspond the output of DDS to the input of IFFT. For example, I know if I choose clock  input of DDS 100 MHz and the pahase width in 8 bits and I want to have an output sin and cos of 10 MHz. The phase increment should be 25.6 using this formula. 

f_out = fs * ph_inc / (2^n)
f_out - output frequency,
fs - clock frequency,
ph_inc - phase increment value,
n - bitwidth of phase increment.

 

Please give any idea in order to configure well these two IP for example to compute an IFFT of 1024. How to configure dds to generate 1024 complex output? please should I make conncetion directly between the output of DDS to input data of IFFT or I should stocke them in file or a ram. Please any clarification. This is my first time that I do a project in FPGA; 

Please for the first time, how to configure these IPs to generate these 1024 outputs. Maybee, it can be a stupid question but I am blocked. I dont know how can do an IFFT of IQ data generated from dds compiler

Thanks a lot

 

[jean]

42 minutes ago, jean said:

Hi, I present my self, I am new a new engineer in FPGA. This is the first time that I use FPGA after university.  I am using DDS compiler V6.0 in order to generate cos and sin which represents the I and Q data. I is the amplitude of cos and Q represents the amplitude of sin. The objective is to compute the IFFT of these generated IQ data using the IFFT core of Xilinx. Please have any idea how configure the DDS compiler and IFFT in order to correspond the output of DDS to the input of IFFT. For example, I know if I choose clock  input of DDS 100 MHz and the pahase width in 8 bits and I want to have an output sin and cos of 10 MHz. The phase increment should be 25.6 using this formula. 

f_out = fs * ph_inc / (2^n)
f_out - output frequency,
fs - clock frequency,
ph_inc - phase increment value,
n - bitwidth of phase increment.

 

Please give any idea in order to configure well these two IP for example to compute an IFFT of 1024. How to configure dds to generate 1024 complex output? please should I make conncetion directly between the output of DDS to input data of IFFT or I should stocke them in file or a ram. Please any clarification. This is my first time that I do a project in FPGA; 

Thanks a lot

 

For the first time, I think to store the generated data, cos and sin but How can I do it