Background:
I am sending 3 channels of digitized 12-bit (soon to be 16-bit) data over "long" distances (thus I will be sending the data using LVDS). I will also be sending a 40 Mhz clock signal over LVDS so in total, that will be 3 data channels + 1 clock (= 4 channels x 2 wires/channel = 8 wires). The data rate is 600-720 Mbps per channel for 12-bit and up to 960Mbps per channel for 16-bit for the data lines.
Question(s):
I would like to use the HDMI connector on the Z7-20 board to get the data in. Is that possible? If so, I would appreciate any information as to how to go about doing this. HDMI has a number of LVDS lines (actually TDMS) and I would like to take advantage of the built in hardware to include deserialization of the data and memory storage. TDMS uses 9/10 bit data but I will use 12 bit to 16 bits. Is the data size fixed in hardware or would I be able to configure that? I'm new to FPGAs but can the data get pipelined directly into memory? If so, is there a way to set the bit endianness as it gets stored into memory?
If the above is solvable, I would like to know if I can use both HDMI connectors to do this (I will actually have 2 sensors), both the HDMI in and HDMI out. In theory I just need the data lines and access to memory so I wouldn't think that this would be a problem on the HDMI out as well, but I don't know...which is why I'm asking.
If the above isn't possible, are there any other options? I can make an adapter board and deserialize the data to CMOS/TTL digital IO and use the PMOD or shield connectors to send the data to the FPGA but this would be 12 bits/channel x 3 channels = 36 bits at 40 Mhz, (48 bits for 16 bit data). That doesn't leave me very many (or any) lines for output but if that is my only option, is 40 Mhz considered high speed?
Question
User1234
Hi,
Background:
I am sending 3 channels of digitized 12-bit (soon to be 16-bit) data over "long" distances (thus I will be sending the data using LVDS). I will also be sending a 40 Mhz clock signal over LVDS so in total, that will be 3 data channels + 1 clock (= 4 channels x 2 wires/channel = 8 wires). The data rate is 600-720 Mbps per channel for 12-bit and up to 960Mbps per channel for 16-bit for the data lines.
Question(s):
I would like to use the HDMI connector on the Z7-20 board to get the data in. Is that possible? If so, I would appreciate any information as to how to go about doing this. HDMI has a number of LVDS lines (actually TDMS) and I would like to take advantage of the built in hardware to include deserialization of the data and memory storage. TDMS uses 9/10 bit data but I will use 12 bit to 16 bits. Is the data size fixed in hardware or would I be able to configure that? I'm new to FPGAs but can the data get pipelined directly into memory? If so, is there a way to set the bit endianness as it gets stored into memory?
If the above is solvable, I would like to know if I can use both HDMI connectors to do this (I will actually have 2 sensors), both the HDMI in and HDMI out. In theory I just need the data lines and access to memory so I wouldn't think that this would be a problem on the HDMI out as well, but I don't know...which is why I'm asking.
If the above isn't possible, are there any other options? I can make an adapter board and deserialize the data to CMOS/TTL digital IO and use the PMOD or shield connectors to send the data to the FPGA but this would be 12 bits/channel x 3 channels = 36 bits at 40 Mhz, (48 bits for 16 bit data). That doesn't leave me very many (or any) lines for output but if that is my only option, is 40 Mhz considered high speed?
Thanks in advance.
Link to comment
Share on other sites
0 answers to this question
Recommended Posts
Archived
This topic is now archived and is closed to further replies.