Zybo-Z7-10 project no matching 2017.4 Vivado library

[plu]

We're trying to build from source the base-linux FPGA for Zybo-Z7-10, matching the FPGA provided in the corresponding Petalinux...

https://github.com/Digilent/Zybo-Z7-10-base-linux

https://github.com/Digilent/Petalinux-Zybo-Z7-10?_ga=2.130631759.1389867965.1596815310-20008779.1584747998

 

The problem is Digilent did not archive any 2017.4 Vivado library, which would correspond to the toolchain the base-linux requires.

https://github.com/Digilent/vivado-library/releases?_ga=2.234565598.1389867965.1596815310-20008779.1584747998

 

With the most recent Vivado library, there were 4 mismatching IPs.  With the 2018.2 Digilent Vivado library, 3 of the 4 mismatching library seems to match.  But, the axi_dynclk module from the library does not match what is required by the board's sources.  The module ports/pins (name and numbers) do not match.  The 2016.4 library doesn't work either.

It seems the connections for the axi_dynclk may have been hand-tweaked after the fact, or the reason the 2017.4 library does not exist is because there were problems with it.

 

Has anyone come across this problem and figured out a fix yet?  Perhaps there's some axi_dynclk sources that would match the one needed by the base-linux.

 

We may be forced to go figure out how to adapt the 2018.2 axi_dynclk to the 2017.4 base-linux build, but there's always possibilities of incorrect/improper fixes.

 

Thanks.

 

 

 

[plu]

I tried building this project, which uses the most current Digilent Vivado library, but it suffers the same problem with axi_dynclk.

https://shiroku.net/robotics/setup-zybo-z7-10-hdmi-demo/

 

Obviously, at some point the Vivado library matched the wiring of the project, to allow the HDMI project to build and run.

Sigh...

 

[plu]

Looks like a git checkout of the 11/29/17 archive (just prior to the merge-in of the "standalone" axi_dynclk on 12/05/17) retrieves a version of vivado-library that is close enough to the needed 2017.4.

This gets over the axi-dynclk incompatibility problem.