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Recommend me a FPGA Dev board.


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Hello, all. I'm an aspiring CPU designer, looking to design my first CPUs, have compiler errors, and learn a lot along the way. I finished my first FPGA class this last semester, and I'm hungry for more. The FPGA we used in class was the Digilent Nexys A7. This board worked well for what we did in class, but I would like to upgrade, as I found myself commonly exceeding the number of cells available during experimentation. Here are my working requirements:

 

Must have:

  • At least one Ethernet port, either directly connected, or connected via PHY.  
  • Some sort of EEPROM or non-volatile storage capability
  • Onboard display for de-bugging on the fly. Can be a LCD, 7-segs, LEDs, whatever.
  • Must be around or under 1k$ US
  • Be shipped from North America
  • Internal clocks of at least 50MHz
  • Xilinx-based FPGA
  • If not supported by Vivado web-pak, it must come with a license to synthesize and implement RTL HDLs.

It would be nice to have:

  • Many, many logic cells
  • Three Ethernet ports
  • On-board interfaces (buttons, switches, etc)
  • onboard DIMM slots for RAM,
  • USB programming interface
  • A board listed under Vivado's 'Default parts' menu when creating a project.

 

With these requirements, what would be the best FPGA development board for me?

 

Edited by tuskiomi
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1 hour ago, tuskiomi said:

I'm doing design involving high core counts (64+ cores)

Not sure how you are going to keep all of those cores feed but that's a system problem. The Nexys Video is probably the largest device in your price range that I know of from any FPGA vendor. The Genesys2 is a substantial step up in terms of resources and performance capability but you'll need a license that will expire after a year... this just means that your future development will be node-locked to a particular PC and Vivado tool version. My Genesys2 is locked to Vivado 2016.2 on a WIN7 PC. The nice thing about Xilinx is that licenses are locked to a device so a license for the Genesis2 will also work on the KC705. The limited license by the way is either free with a board purchase or very cheap. The alternative is to spend $3500 or so on a full Vivado tools license and have access to any part.

You will probably want a lot of BRAM which the KC325T has in abundance.

A good strategy for this kind of project, if you have a limited budget, is to be content with developing parts of a very large project instead of trying to do the whole thing.

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I should also point out that the Genesys2 has a very nice HPC FMC connector so you can add a USB 3.0 interface if you need to transfer large amounts of data between your FPGA platform and a PC. More information to process. You won't find an FPGA board with more FPGA resources than the Genesys2 for anything even close to the 'poor slob highest price' point.

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 Hi,

>> I finished my first FPGA class this last semester, ... looking to design my first CPUs ... I found myself commonly exceeding the number of cells available during experimentation.

let me offer an opinion and I'll keep it short but I suspect you're heading into a dead end, the lesson to be learned eventually - after spending too much money and too much time - being that FPGA technology doesn't really scale this way. For example realizing that you need $1000 hardware to do a job that a Raspberry Pi could do better for $50.

If you intend to design for ASIC and plan to use the FPGA for emulation, forget I said anything. But, after finishing "the first FPGA class", this seems unlikely as it's highly specialized niche business. Otherwise a reminder, focusing on the "interesting problem" in research is pretty much a guarantee that you're missing that dull, obvious practical problem that shouldn't exist in the first place but kills your idea (whatever that is) in reality. The question I'd ask myself is, "why am I running out of cells" and maybe "does anybody actually USE a custom-designed FPGA soft core CPU outside a research-driven environment and why not".

As a rule of thumb, if a design grows accidentally large you can be pretty sure it will also turn out to be slow. A typical student mistake would be to design around variable bitshifts because that's how you write efficient code on a simple, integer CPU and the HDL code looks harmless. But on an FPGA it's just the opposite, it becomes an any-bit-to-any-bit matrix which is both large and slow from its depth of logic levels. E.g. a single 32-bit barrel shifter will be a significant contributor to the logic count of a simple CPU like J1B. Using a large FPGA may hide the size issue but won't recover lost speed, it's a fundamental design issue  that needs to be fixed elsewhere.

And FYI: There are clock management tiles that will give you any frequency you choose so the input clock frequency is generally not that important. Maybe you have reasons for your "requirement" but not being aware of MMCM/PLL cells is very common at "first FPGA class" level so I'm pointing it out.

Edited by xc6lx45
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3 hours ago, tuskiomi said:

With these requirements, what would be the best FPGA development board for me?

Those are some set of requirements.

You aren't going to find a FPGA board with 3 Ethernet ports. That's a lot of clock domains by the way.

The Nexys Video has a spacious Artix 200T so it doesn't require any special license that will expire. It has external memory, flash, a parallel USB port. It's well under $1K.

For more gates you're talking Kintex and this will require a license as the devices that are supported for free are non-existent. Unfortunately, Xilinx and Digilent seem to be abandoning logic only devices so your limited options will become even more limited in the future.

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A reasonable sized FPGA should be able to absorb your CPU designs and the Nexys Video is a pretty capable board.

Is there any chance of including a "show_utilization -hierarchical" where we can review things?

My feeling is that with a bit of though a lot of FFs and LUTRAMs could be revised to use more efficient, denser resources.

Have you done much reading of the 7-series user guides, and the style guides that help you to write code that infer the most effective resources? 

 

Edited by hamster
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5 hours ago, zygot said:

Not sure how you are going to keep all of those cores feed but that's a system problem. The Nexys Video is probably the largest device in your price range that I know of from any FPGA vendor. The Genesys2 is a substantial step up in terms of resources and performance capability but you'll need a license that will expire after a year... this just means that your future development will be node-locked to a particular PC and Vivado tool version. My Genesys2 is locked to Vivado 2016.2 on a WIN7 PC. The nice thing about Xilinx is that licenses are locked to a device so a license for the Genesis2 will also work on the KC705. The limited license by the way is either free with a board purchase or very cheap. The alternative is to spend $3500 or so on a full Vivado tools license and have access to any part.

You will probably want a lot of BRAM which the KC325T has in abundance.

A good strategy for this kind of project, if you have a limited budget, is to be content with developing parts of a very large project instead of trying to do the whole thing.

I love this advice. In short the application is a generic RISC V core in which there are many smaller RISC CPUs which are simpler, and support much less instructions (no access to ctrl regs, half precision multiply, etc). i want to experiment with branch prediction, vector instructions, and simple loop compression, as well as what you mentioned with feeding algorithms. one step at a time though, and ive been modifying an open source risc V processor for the last few months, and at this point i cannot make any more progress without physical testing, as vivado doesnt support some vhdl 2008 features during simulation.

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i want to experiment with branch prediction, vector instructions, and simple loop compression, as well as what you mentioned with feeding algorithms

Great! When you figure this all out I know of a former world leader in CPUs that can't figure out how to optimize a 40 year old architecture without introducing horrible security loopholes. After compensating with myriads of software bandages all of the magic disappears. It can't be fun working at a company that used to kick the competition around for fun and now is getting sand kicked into its face by the one survivor.

The Genesys2, when it becomes available again, is a nice platform for the price with lot's of capability. If you can afford it my view is that it's a better deal than the Nexys Video.

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1 hour ago, zygot said:

Great! When you figure this all out I know of a former world leader in CPUs that can't figure out how to optimize a 40 year old architecture without introducing horrible security loopholes. After compensating with myriads of software bandages all of the magic disappears. It can't be fun working at a company that used to kick the competition around for fun and now is getting sand kicked into its face by the one survivor.

The Genesys2, when it becomes available again, is a nice platform for the price with lot's of capability. If you can afford it my view is that it's a better deal than the Nexys Video.

Okay, processor company jabbing aside ;-), I'd like to introduce my other application.

Years ago I created a program which takes trained neural networks, and exports them to HDL -like formats (think lots of LUTs). Eventually, I'd like to take these neural networks, and if resources allow, place them directly into the fpga, which would allow a trained network to be executed in just a small number of clock cycles, instead of multiple hundreds. 

Trouble is, neural networks require lots of resources. One neuron will take up 8 LUT inputs, which is silly when you have thousands of neurons, and then you need to consider a memory loader, etc. 

 

In any case, lots of LUTs are preferred, and I think the genesys 2 is my board. Trouble is waiting.

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2 hours ago, zygot said:

The Genesys2, when it becomes available again, is a nice platform for the price with lot's of capability. If you can afford it my view is that it's a better deal than the Nexys Video.

It's in stock at Digikey right now.

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18 minutes ago, tuskiomi said:

Okay, processor company jabbing aside ;-),

But it's so satisfying! No really, the unnamed company in question is a study in how companies suffer from their own scorch and burn competitive strategies.   Really, competition is good for everyone, including those who have an affinity toward monopolistic control over an industry. It's unfortunate that we've reverted back to the bad old 19th century as a society. When I make my cheap shots I take it seriously. Know you history future tech overlords!

Now to you other application. The perfect board for you might be the Terasic C5P or as it's now know the OpenVino start platform. It's designed to be a PCIe PC board and the GT version has 4 lanes of Gen2 PCIe so it's more of an extension to your PC. Your neural network application is precisely what the board is designed to do. I'm no expert in neural networks but my impression is that the typical FPGA isn't ideal for applications though might be swell as a platform for exploring ways to speed up the process. The board is relatively cheap and has good Linux and Windows driver support. The Cyclone V isn't up there with the Kintex 325T in resources but you should at least check it out. If only there was a similar board for us Xilinx users....

 

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7 minutes ago, asmi said:

Does digikey honor digilent academic discounts

I'm pretty sure that you can get a license voucher from Digilent even if you purchase the board from a distributor.. get an answer from Digilent to verify.

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About PCIe FPGA boards. I should point out that PCIe boards are detected during BIOS boot so you can't re-configure the entire FPGA from a PC application and keep running... you have to reconfigure and reboot. For a price you can do partial reconfiguration on the fly though and have a true application accelerator. It's just something to know about before jumping on board.

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8 minutes ago, zygot said:

I'm pretty sure that you can get a license voucher from Digilent even if you purchase the board from a distributor.. get an answer from Digilent to verify.

He's probably talking about academic discounts, not license vouchers.

Edited by asmi
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8 minutes ago, asmi said:

He's probably talking about academic discounts, not license vouchers.

Didn't consider this but even more reason to send an email to @JColvinor someone else... gee I think that I just did it for you.

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49 minutes ago, tuskiomi said:

which would allow a trained network to be executed in just a small number of clock cycles, instead of multiple hundreds.

I think I see where this is heading ... there are essentially two design corners: a completely systolic, one-cycle-per-operation architecture, and a CPU-based architecture where everything is funneled through a single ALU.

Both extremes are fairly trivial to implement, the former going through the roof with its resource usage and you will have a hard time feeding data in to actually use it.  The latter (=run C code) having its lunch eaten by any "hard" CPU core on the same technology node.

The design space in-between is where it gets interesting for FPGA, but also much more challenging.

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2 minutes ago, xc6lx45 said:

I think I see where this is heading ... there are essentially two design corners: a completely systolic, one-cycle-per-operation architecture, and a CPU-based architecture where everything is funneled through a single ALU.

Both extremes are fairly trivial to implement, the former going through the roof with its resource usage and you will have a hard time feeding data in to actually use it.  The latter (=run C code) having its lunch eaten by any "hard" CPU core on the same technology node.

The design space in-between is where it gets interesting for FPGA, but also much more challenging.

Good to see that I'm starting with the trivial implementation.

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Hello @tuskiomi (and other curious readers on this thread),

I confirmed with our Sales Manager that Digi-Key does not do any academic discounts (and for reference, very few distributors will do academic discounts; the only one that I am aware of is Trenz Electronics, but that is only for German customers. But I don't think they have any Genesys 2's in stock even if you do happen to be based in Germany).

I am waiting for confirmation our FPGA Product Manager that the timeline listed on the Genesys 2 store page, i.e. boards slated to be shipping again from the Digilent store directly in September 2020, is the most up to date information.

Edit: got confirmation that the September 2020 date on the store page is still accurate.

Thank you,
JColvin

Edited by JColvin
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If you can wait a few months to make a purchase and can get an academic discount that's obviously the cheaper way to go.

Even at $1K per pop the Genesys2 is a fantastic value and heavily subsidized by Xilinx. If you doubt this then, while you're at the distributor's site do a search for the XC7K325TFFG900C-2 part and compare the price. Note the lead times. If you think that you're at the wrong distributor then try Avnet or one of the bigger distributors. It's unfortunate but Xilinx seems to have moved on to other newer families for scheduling fab orders. I don't know of anything close to the Genesys2 on the market at the normal retail level. Kintex and UltraScale Kintex are great niches in the FPGA marketplace... if only small developers could buy them and make a profit selling Kintex based products...

I wonder if Xilinx regrets going fabless, yet...

Edited by zygot
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20 hours ago, tuskiomi said:

Good to see that I'm starting with the trivial implementation.

Yea but it's not trivial in a sense of being the first point on a straight line that evolves somewhere. More like starting F1 racing car design with a novel horse carriage - it'll take some clever talking to get your point across later that this isn't just solution-looking-for-a-problem thinking.

If you're running into resource issues already on a toy design, it seems like a dead giveaway that your thinking will not scale to real-world problems

Edited by xc6lx45
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