Inter-board Data Transfer Project


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Do you need a board to board data interface because you've run out of IO or need a high speed PC interface? Interested in learning about how to deal with multiple clock domains? Just want to learn VHDL or the HDL design source flow? Do you want to stream your Arty A7 with ADC PMOD samples to a PC but don't have a suitable interface? Keep reading...

Here's a project to try out and study. Zygot revisits the differential PMOD to find a use for it.

Is this a new Differential PMOD Challenge?

There's only one way to find out.

HighSpeedUartInf_Rev1.zip

Edited by zygot
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Zygot, you're an idiot... I've already changed one line of code and improved that data rate by 16% to about 20 MB/s... love, the neurons in zygot's brain that are on speaking terms.

Can anyone else find Zygot's silly mistake ?

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I'm not too experienced with VHDL so I'm probably wrong, but I did see that the N number of 8-bit words listed between the HsSerializer entity listed in HsSerializer.vhd and the HsSerializer component in the HsUartTx.vhd file did not match. But I'm not sure if that difference contributes to the 16% improvement you found.

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1 hour ago, JColvin said:

But I'm not sure if that difference contributes to the 16% improvement you found.

Nope. But you're on the right track... go up one level on the hierarchy. It's a goofy mistake and not obvious if you don't run the simulation to see how the design works.

It's odd how one can read code and be bothered by something, but not process it it at all, only to have it sack you in the head while doing something unrelated. I'd hate to see a schematic for the wiring of my brain....

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I can say this. The basic design concept is quite robust. The project as submitted works at about 20 MB/s but I've changed the clocking and run a 2 board setup at over 30 MB/s. Still, I'd like to see a better design approach.

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1 hour ago, JColvin said:

I did see that the N number of 8-bit words listed between the HsSerializer entity listed in HsSerializer.vhd and the HsSerializer component in the HsUartTx.vhd file did not match.

OK... this just sank in. You've uncovered a commentary bug. My first attempt at implementing the project was going to be be an 8-pin full duplex UART. This changed and I missed changing the HsUartTx.vhd text. As it turns out N is defined higher in the hierarchy as 13 because the demo uses 26-bit words. The 8-bit comment was for an earlier 8-bit UART data word as I was debugging the design and should have disappeared.

Thanks for the catch. I've already fixed it. BTW the design as posted really is working on my test bench between a Nexys Video and Genesys2.

One of the interesting features of the design is that it can accommodate almost any word width to fit any application with just one generic parameter change.

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6 hours ago, falcon98 said:

Can you confirm what rate could you get from this code.

As submitted it does almost 17 MB/s and it should work with any boards having differential PMODs. This is with 8.5" flying leads. I modified one line of code that increased this to 20 MB/s but am hoping that someone else finds it before the next, corrected, version is published. The design is specifically for differential pcb traces and a board that only has 3.3V IO banks rendering LVDS inappropriate.For ideas on using TMDS_33 see the Differential PMOD Challenge project in the Project Vault area. TMDS_33 didn't meet the criteria set for this project.

You can certainly change the serializer/deserializer components to shift one bit at a time and output a 1-bit signal.  There are a number of possible alternate design approaches. No doubt that there's a better one that I didn't pursue yet.

I changed the clocking of the published code to increase the maximum bit rate from 25 Mb/s per channel to 40 Mb/s and that also ran without errors on my setup at about 31 MB/s. I suspect that the design can work at even higher rates. For a real interface I'd probably add series termination on the driver end to reduce overshoot. But, that is out of scope for this project.

The design could work for the CMODs as their IO doesn't have 200 ohm series resistors. But I'd likely use a different design for that board. This project is more of a conceptual exercise than working implementation; though it does work on hardware and requires one to consider the same things as a real implementation would.

The design would work with standard PMODs though at lower data rates, but then most people already are using those.

The basic purpose of the design is to allow boards with the almost useless differential PMODs but without a high speed PC interface, like the Arty-A7 to stream data at a moderate rate to a PC. That end of the project will be forthcoming, though possibly as a different project.

One advantage over other serial interfaces like USB is the low latency and ow overhead. It's also faster than 10/100 Ethernet by a wide margin and significantly less complex. Even if you packetize the data you can do it more efficiently with this design than Ethernet. Obviously, it isn't as flexible or a replacement for Ethernet. Standard serial interfaces also don't support an arbitrary word size like this design does.

Like all of my Project Vault submissions this one is more about encouraging learning than solving specific problems. Like the Differential PMOD Challenge, I'm hoping for others to show of their design chops with a better concept. A bit of competition is always fun and encourages better thinking.

[edit] At 31 MB/s the interface is in the same ballpark as realistic 1GbE, which has a peak data rate of 125 M bytes/s. Once you add overhead and typical issues 1GbE falls to a more attainable 30-40 MB/s.

Edited by zygot
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6 hours ago, falcon98 said:

i will try this on Spartan 3 boards

Not a lot of people realize that the Spartan 3 family had IO features not universally available to Series 7 devices. If I were doing a Spartan 3 design then this would have a quite different implementation.

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