According to the guide, I simply need to leave the clock high for 50 microseconds. I've tried various permutations of manipulating the clock and data line on the rising/falling edge, but not a single blip that I haven't caused. I'm using waveforms to see if any of the lines move. Only my div clock does (10Khz).
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
entity KeyMain is
Port (clk : in STD_LOGIC;
USB2_CLK : inout STD_LOGIC;
USB2_DATA : inout STD_LOGIC;
led : out STD_LOGIC_VECTOR(7 downto 0);
dio0 : out STD_LOGIC;
dio1 : out STD_LOGIC;
dio2 : OUT STD_LOGIC);
end KeyMain;
architecture Behavioral of KeyMain is
component clk_div is
port ( CLK_IN : in STD_LOGIC;
CLK_OUT : out STD_LOGIC);
end component;
signal key_buff : STD_LOGIC_VECTOR(7 downto 0) := "10000001";
signal buff_counter : unsigned(3 DOWNTO 0) := "0000";
signal temp : STD_LOGIC := '0';
signal step_counter : unsigned(3 DOWNTO 0) := "0000";
signal div_clk : STD_LOGIC;
begin
clk_div_inst : clk_div
port map(
CLK_IN => clk,
CLK_OUT => div_clk);
process(div_clk, USB2_CLK)
begin
if falling_edge(USB2_CLK) then
if step_counter = 1 then
if buff_counter > 10 then
buff_counter <= "0000";
--key_buff <= "00000000";
else
buff_counter <= buff_counter + 1;
end if;
if buff_counter > 0 then
key_buff(to_integer(buff_counter - 1)) <= USB2_DATA;
end if;
end if;
end if;
if falling_edge(div_clk) then
if step_counter = 0 then
USB2_CLK <= '1';
--USB2_DATA <= '1';
--elsif step_counter = 1 then
--USB2_CLK <= '0';
--USB2_DATA <= '0';
--elsif step_counter = 2 then
--USB2_DATA <= '0';
end if;
if step_counter /= 1 then
step_counter <= step_counter + 1;
end if;
end if;
end process;
led <= key_buff;
dio0 <= USB2_CLK;
dio1 <= USB2_DATA;
dio2 <= div_clk;
end Behavioral;
Question
CPerez10
I know this topic has been started before, but I wanted to program my own driver to communicate with the keyboard as a learning experience.
Currently trying to get data from my USB keyboard or getting the clock going. I used this guide: http://www.burtonsys.com/ps2_chapweske.htm
According to the guide, I simply need to leave the clock high for 50 microseconds. I've tried various permutations of manipulating the clock and data line on the rising/falling edge, but not a single blip that I haven't caused. I'm using waveforms to see if any of the lines move. Only my div clock does (10Khz).
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_unsigned.all; entity KeyMain is Port (clk : in STD_LOGIC; USB2_CLK : inout STD_LOGIC; USB2_DATA : inout STD_LOGIC; led : out STD_LOGIC_VECTOR(7 downto 0); dio0 : out STD_LOGIC; dio1 : out STD_LOGIC; dio2 : OUT STD_LOGIC); end KeyMain; architecture Behavioral of KeyMain is component clk_div is port ( CLK_IN : in STD_LOGIC; CLK_OUT : out STD_LOGIC); end component; signal key_buff : STD_LOGIC_VECTOR(7 downto 0) := "10000001"; signal buff_counter : unsigned(3 DOWNTO 0) := "0000"; signal temp : STD_LOGIC := '0'; signal step_counter : unsigned(3 DOWNTO 0) := "0000"; signal div_clk : STD_LOGIC; begin clk_div_inst : clk_div port map( CLK_IN => clk, CLK_OUT => div_clk); process(div_clk, USB2_CLK) begin if falling_edge(USB2_CLK) then if step_counter = 1 then if buff_counter > 10 then buff_counter <= "0000"; --key_buff <= "00000000"; else buff_counter <= buff_counter + 1; end if; if buff_counter > 0 then key_buff(to_integer(buff_counter - 1)) <= USB2_DATA; end if; end if; end if; if falling_edge(div_clk) then if step_counter = 0 then USB2_CLK <= '1'; --USB2_DATA <= '1'; --elsif step_counter = 1 then --USB2_CLK <= '0'; --USB2_DATA <= '0'; --elsif step_counter = 2 then --USB2_DATA <= '0'; end if; if step_counter /= 1 then step_counter <= step_counter + 1; end if; end if; end process; led <= key_buff; dio0 <= USB2_CLK; dio1 <= USB2_DATA; dio2 <= div_clk; end Behavioral;
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