For PWM_2.0 , the System Verilog code source file ip/PWM_2.0/hdl/PWM_AXI.sv mixed a blocking and non-blocking assignment in a combinatorial process. My understanding is that all assignments in a combinatorial block should be blocking assignment so that Xilinx Vivado does not infer latches. It was also necessary to update the Makefile to be compatible with Vivado 2020.1 .
Additionally, the C source file ip/Pmods/PmodSF3_v1_0/drivers/PmodSF3_v1_0/src/intc.h included a Xilinx C header with camel case name instead of lowercase. This error does not show on Windows 10, but does show on Linux where the file system is case-sensitive.
Finally, Pmod SF3 and Pmod CLS required updating their XSPI driver to not overwrite in the GNU AR contents with an outdated XSPI driver.
I would recommend updating Pmod SF3 to use a configuration of the Xilinx AXI QSPI IP that is configured for a 256 Beat FIFO instead of a 16 Beat FIFO, and to specify that the memory type is Micron.
Regards,
Tim S.
commit 238b8ed08331473a288c0ca3522ca0b6a5e4423a
Author: Timothy Stotts <timothystotts08@gmail.com>
Date: Thu Jul 30 14:07:27 2020 -0400
The PmodCLS_v1_0 was repackaged under Linux as the Group File Wizard indicated required merging.
ip/Pmods/PmodCLS_v1_0/component.xml
commit a435c1ba6294fdff7742bcf465c27fda11ac962b
Author: Timothy Stotts <timothystotts08@gmail.com>
Date: Thu Jul 30 14:05:07 2020 -0400
The include xscugic.h must be specified in all lowercase to successfully compile on case-sensitive file systems, such as Linux EXT4. This was corrected in intc.h of IP PmodSF3_v1_0
ip/Pmods/PmodSF3_v1_0/component.xml
ip/Pmods/PmodSF3_v1_0/drivers/PmodSF3_v1_0/src/intc.h
commit 52b2d6f3801f5601f6a8fc7ad709d2041dc3f557
Author: Timothy Stotts <timothystotts08@gmail.com>
Date: Thu Jul 30 14:02:53 2020 -0400
The SystemVerilog source for PWM_2.0 contained a mix of blocking and non-blocking assignment, resulting in an inferred latch. This was corrected. The PWM_2.0 was repackaged with the updated source file PWM_AXI.sv .
ip/PWM_2.0/component.xml
ip/PWM_2.0/hdl/PWM_AXI.sv
commit a7d5c144faa4e64b3a8667bfe278733643b55502
Author: Timothy Stotts <timothystotts08@gmail.com>
Date: Wed Jul 29 23:28:23 2020 -0400
The PWM 2.0, PmodCLS, PmodSF3 drivers were updated for usage on the Zybo Z7-20 with Vivado 2020.1 .
ip/PWM_2.0/component.xml
ip/PWM_2.0/drivers/PWM_v1_0/src/Makefile
ip/Pmods/PmodCLS_v1_0/component.xml
ip/Pmods/PmodCLS_v1_0/drivers/PmodCLS_v1_0/src/xspi.c
ip/Pmods/PmodCLS_v1_0/drivers/PmodCLS_v1_0/src/xspi.h
ip/Pmods/PmodCLS_v1_0/drivers/PmodCLS_v1_0/src/xspi_i.h
ip/Pmods/PmodCLS_v1_0/drivers/PmodCLS_v1_0/src/xspi_l.h
ip/Pmods/PmodCLS_v1_0/drivers/PmodCLS_v1_0/src/xspi_options.c
ip/Pmods/PmodCLS_v1_0/drivers/PmodCLS_v1_0/src/xspi_selftest.c
ip/Pmods/PmodCLS_v1_0/drivers/PmodCLS_v1_0/src/xspi_stats.c
ip/Pmods/PmodCLS_v1_0/src/PmodCLS_axi_quad_spi_0_0/PmodCLS_axi_quad_spi_0_0.xci
ip/Pmods/PmodCLS_v1_0/src/PmodCLS_axi_quad_spi_0_0/PmodCLS_axi_quad_spi_0_0.xml
ip/Pmods/PmodCLS_v1_0/src/PmodCLS_pmod_bridge_0_0/PmodCLS_pmod_bridge_0_0.xci
ip/Pmods/PmodCLS_v1_0/src/PmodCLS_pmod_bridge_0_0/PmodCLS_pmod_bridge_0_0.xml
ip/Pmods/PmodSF3_v1_0/component.xml
ip/Pmods/PmodSF3_v1_0/drivers/PmodSF3_v1_0/src/PmodSF3.c
ip/Pmods/PmodSF3_v1_0/drivers/PmodSF3_v1_0/src/PmodSF3.h
ip/Pmods/PmodSF3_v1_0/drivers/PmodSF3_v1_0/src/intc.c
ip/Pmods/PmodSF3_v1_0/drivers/PmodSF3_v1_0/src/xspi.c
ip/Pmods/PmodSF3_v1_0/drivers/PmodSF3_v1_0/src/xspi.h
ip/Pmods/PmodSF3_v1_0/drivers/PmodSF3_v1_0/src/xspi_i.h
ip/Pmods/PmodSF3_v1_0/drivers/PmodSF3_v1_0/src/xspi_l.h
ip/Pmods/PmodSF3_v1_0/drivers/PmodSF3_v1_0/src/xspi_options.c
ip/Pmods/PmodSF3_v1_0/drivers/PmodSF3_v1_0/src/xspi_selftest.c
ip/Pmods/PmodSF3_v1_0/drivers/PmodSF3_v1_0/src/xspi_stats.c
ip/Pmods/PmodSF3_v1_0/src/PmodSF3_axi_quad_spi_0_0/PmodSF3_axi_quad_spi_0_0.xci
ip/Pmods/PmodSF3_v1_0/src/PmodSF3_axi_quad_spi_0_0/PmodSF3_axi_quad_spi_0_0.xml
ip/Pmods/PmodSF3_v1_0/src/PmodSF3_pmod_bridge_0_0/PmodSF3_pmod_bridge_0_0.xci
ip/Pmods/PmodSF3_v1_0/src/PmodSF3_pmod_bridge_0_0/PmodSF3_pmod_bridge_0_0.xml
commit 73d14c6899228595e853cfa50ad6f2817ffb34a4
Merge: a33ba97 8b2d675
Author: Timothy Stotts <timothystotts08@gmail.com>
Date: Wed Jul 29 15:54:44 2020 -0400
Merge remote-tracking branch 'remotes/origin/feature/pmod_update' into zybo-z7-20-vivado-2020.1
Question
Tim S.
Hi. I'd liike to report a few bugs I discovered in the vivado-library IP.
The bug fixes are committed to https://github.com/timothystotts/vivado-library in the branches.
git log remotes/origin/zybo-z7-20-vivado-2020.1 --name-only
For PWM_2.0 , the System Verilog code source file ip/PWM_2.0/hdl/PWM_AXI.sv mixed a blocking and non-blocking assignment in a combinatorial process. My understanding is that all assignments in a combinatorial block should be blocking assignment so that Xilinx Vivado does not infer latches. It was also necessary to update the Makefile to be compatible with Vivado 2020.1 .
Additionally, the C source file ip/Pmods/PmodSF3_v1_0/drivers/PmodSF3_v1_0/src/intc.h included a Xilinx C header with camel case name instead of lowercase. This error does not show on Windows 10, but does show on Linux where the file system is case-sensitive.
Finally, Pmod SF3 and Pmod CLS required updating their XSPI driver to not overwrite in the GNU AR contents with an outdated XSPI driver.
I would recommend updating Pmod SF3 to use a configuration of the Xilinx AXI QSPI IP that is configured for a 256 Beat FIFO instead of a 16 Beat FIFO, and to specify that the memory type is Micron.
Regards,
Tim S.
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