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MIPI D-PHY configuration for 4 pcam


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Hi all,

I download the "ZedBoard-FMC-Pcam-Adapter-Dual-Camera-2018.2-1" and open it on vivado 2018.

There are four MIPI D-PHY (A,B,C,D). In #A, we have a RxByteClk = 84MHz, which can be derived from total data rate =1344Mbps.

However, when i check the configuration of #B,#C,#D, all of them have RxByteClk = 25MHz. 

Can I know how the difference or how the 25MHz be derived?

 

Thanks.

BR

 

001_dphy_a.png

001_dphy_b.png

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It could be that 25MHz is some propagated value but starting with 100MHz MIPI clock from MIPI_DPHY_Receiver_ooc.xdc (out-of-context synthesis) and 84MHz is calculated from a MIPI clock constrained in the top-level design.

I think this is missing constraints bug in the demo projects. We will look into it.

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Hi,

Sorry it took so long but we have found a fix for this problem and I'll demonstrate it using screenshots.

First of all make sure you have your Block Design opened in a Tab in Vivado. Then go to File -> Export -> Block Design and save it in the default location preferably or wherever else you want. This operation generates and exports the Tcl script that can be used to recreate this block design.

image.png.9ce4e83605de31e6ff39a2c45dbaeef2.png

Now go to the Sources tab, right-click on the wrapper and select Remove File from Project..., also make sure you check the Also delete the project local file/directory from disk and press OK.

image.png.b8b8fb46085b2294f9c7907a9d2aefd7.png

image.thumb.png.c4b12ce0d30698a2b18f84eebb9d02d9.png

When prompted make sure the Automatically pick new top module option is selected and press OK.

image.png.94a99d12d83181067034f4ca7a84d57d.png

You'll now need to delete the current block design so make sure you have exported it to a memorable location such as the default location, which should be the vivado_proj folder.

image.png.017ab0109f114d8f69cf9748f81b0a57.png 

This next step requires you to open the system.tcl file which will be used to recreate the block design and edit it with your text editor of choice.

image.png.46b6d64b8ac7b3f452a2adce5cb79c03.png

image.thumb.png.2c75119ce383587990ca687d5f194c40.png

Go to line 244 and copy it along with lines 245 and 246 and paste them after each set dphy_*_hs_clock line so it looks like in the following screentshot:

image.thumb.png.290c5f099c723728bdf736edbe7cc1b9.png 

Make sure you save the file.

What you have to do now is to go to Tools -> Run Tcl Script..., find the system.tcl file which you've modified earlier using a text editor and press OK.

image.png.773298928a862596ba3639fba86f8437.png

image.thumb.png.50545c18b3f1b26ad5fc2f88cd887c05.png

Wait for Vivado to finish running the Tcl script and generating the new block design.

Right click on the new block design and select Create HDL Wrapper..., when prompted make sure the Let Vivado manage wrapper and auto-update option is selected and then press OK.

image.png.c6b7b779d51f571724ea936fb3a3c36f.png

image.png.c8c6944421f3d913d61840e5c0f39c30.png

Right click on the newly created wrapper and choose Set as Top.

image.png.26f57f3291e226bfe8242a3fa4d1ccff.png

And now to demonstrate that it actually worked I'll include a screenshot of the MIPI_D_PHY_RX_C IP and if you look at the properties of pin RxByteClkHS you can see that it now says that it's frequency is indeed 84 MHz just like for the MIPI_D_PHY_RX_A IP.

image.png.c3ece68728ade2dff899ccec3cd8cdf2.png

We have found another thing wrong with the project that can easily be fixed by opening the timing.xdc in Vivado's own text editor like so:

image.png.e9f36e5da1b08bfbafea89757294a31a.png

Now go to line 20 of timing.xdc and write dphy_*_hs_clock_clk_p after get_ports.

image.png.37ff5c4b21b4ff2e3bf232c6fba0fb95.png

Ok, this should be all, you can save the timing.xdc file as well as the whole project and generate a new Bitstream.

 

 

 

 

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