Vivado error with Genesys ZU UltraScale Board file

[BT12]

We just bought a Genesys ZU UltraScale board from you. I tried to create a project using Vivado 2018.2 (we have to use this version) and your board files (downloaded from your web site). After adding your board IP ZYNQ UltraSCALE+ (only one IP) in Vivado, and clicking "Run Block Automation", we got 2 error messages, while for Xilinx evaluation board we didn't get any error message at the same step. Any help would be appreciated.

[JColvin]

Hi @BT12,

I apologize for the delay.

Our projects that we have for the Genesys ZU on our GitHub, https://github.com/digilent?q=genesys+zu&type=&language=, are designed to work with 2019.1, not 2018.2, though the board files should not be picky about the Vivado version.

What errors do you get in the during the Run Block Automation process? And what Xilinx evaluation board are you referring to?

Thanks,
JColvin