Hey guys. Still in the noob state where I'm overlooking something simple, but I've tried searching quite a bit on the web to no avail on using the block RAM properly. I use the IP core generator to create a 32x64512 bit block RAM. I then created a simple example that should light my LEDs with the contents I recently wrote into the RAM. No lights light up. Here's the code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity MainSPI is
Port ( clk : in STD_LOGIC;
led : out STD_LOGIC_VECTOR (7 downto 0));
end MainSPI;
architecture Behavioral of MainSPI is
component Block_RAM
port(
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR(0 downto 0);
addra : in STD_LOGIC_VECTOR(15 downto 0);
dina : in STD_LOGIC_VECTOR(31 downto 0);
douta : out STD_LOGIC_VECTOR(31 downto 0)
);
end component;
signal flip1 : STD_LOGIC := '0';
signal flip2 : STD_LOGIC := '0';
signal ram_addr : STD_LOGIC_VECTOR(15 downto 0) := "0000000000000000";
SIGNAL write_enable : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal ram_write : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal ram_read : STD_LOGIC_VECTOR(31 DOWNTO 0);
begin
ram_instance : Block_RAM
port map(
addra => ram_addr,
wea => write_enable,
dina => ram_write,
douta => ram_read,
clka => clk
);
process(clk)
begin
if rising_edge(clk) then
if flip1 = '0' then
write_enable <= "1";
ram_addr <= "0111110000000000";
ram_write <= "10101010111111110000100011101111";
flip1 <= '1';
end if;
if flip2 = '0' and flip1 <= '1' then
write_enable <= "0";
ram_addr <= "0111110000000000";
led <= ram_read(11 downto 4);
flip2 <= '1';
end if;
end if;
end process;
end Behavioral;
Question
CPerez10
Hey guys. Still in the noob state where I'm overlooking something simple, but I've tried searching quite a bit on the web to no avail on using the block RAM properly. I use the IP core generator to create a 32x64512 bit block RAM. I then created a simple example that should light my LEDs with the contents I recently wrote into the RAM. No lights light up. Here's the code:
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