HELP vending machine verilog

[Sam36]

i'm beginner starting to learn verilog code and i'm lost 

module vm(
    //Output Declaration, to be completed...
    output dp,
    //To be populated...
    output [3:0] an,  //4-bit anode control
    output [0:6] seg, //7-seg: abcdefg (seg[0] is 'a') - reversed to suit module quad_seven_seg
    output reg [2:0] led,
    output reg [3:0] dig3, dig2, dig1, dig0, //Put here for observation in simulation 
    output reg [1:0] current_state=0,        //Put here for observation in simulation 
    
    //Input Declaration, to be completed...
    input clk,
    input [2:0] sw,
    input btnU, btnL, btnD, btnC
    //To be populated...
    
    );

/********************************
*** Signals Declaration
********************************/
    //Constants:
//    parameter max_count = 50_000_000;    //0.5 seconds count limit 50_000_000; Simulation value can be 5
    parameter max_count = 5;    //0.5 seconds count limit 50_000_000; Simulation value can be 5
    parameter IDLE = 0, COIN = 1, VEND = 2, REFUND = 3;    //State machine definition
    //To be populated...
    
    //Signals:
    wire S10c, S20c, S50c, Cancel; //From PB_Pulse_Generator
    reg [2:0] patt = 0;
//    reg [1:0] current_state = 0;  //Changed to output for observation in simulation
    reg [1:0] next_state = 0;
    reg [31:0] count = 0;    //Count variable
    reg trig = 1'b0;          //1-clock pulse trigger

//    reg [3:0] dig3, dig2, dig1, dig0; //Changed to output for observation in simulation
    
    reg [9:0] money = 0; //Max 1023
    reg [3:0] counter = 0; // Max 15 --> x 0.5s = 7.5s
    reg [2:0] item_selected;

/********************************
*** Sub-Module Instantiation
********************************/
    quad_seven_seg display(//Port mapping:
        clk,
        dig3, dig2, dig1, dig0,  //4 BCD digits - each 4-bit
        an,  //4-bit anode control
        seg, //7-seg: abcdefg
        dp    
    );
       
    PB_Pulse_Generator PB1(.clk(clk), .PB(btnU), .pulse(S10c));
    //To be populated...
    PB_Pulse_Generator PB2(.clk(clk), .PB(btnL), .pulse(S20c));
    PB_Pulse_Generator PB3(.clk(clk), .PB(btnD), .pulse(S50c));
    PB_Pulse_Generator PB4(.clk(clk), .PB(btnC), .pulse(Cancel));
    
/********************************
*** Combinational Logic
********************************/
    //To be populated...
      always@(posedge clk)
      case (current_state)       
          IDLE : 
              begin
                     
              end // of case IDLE -------------------
              
          COIN : 
              begin
 
              end // of case COIN ----------------------
             
          VEND : 
            begin
                
            end // of case VEND -----------------------
            
          REFUND : 
            begin

            end // of case REFUND ---------------------

          default: 
            begin
            end
      endcase

    
/********************************
*** Sequential Logic
********************************/
    /*** 0.5 Second Counting Logic ***/
    always @(posedge clk) begin
        if (count >= max_count) begin
            count <= 0;
            trig <= 1'b1; // trig=1 for 1 clk every 0.5 s
        end
        else begin
            count <= count + 1;
            trig <= 1'b0;
        end
    
      
     // The present "next_state" will become
     // the "current_state" in next clock cycle:
        current_state <= next_state; 
    end
    
endmodule
 

...............................

//                  Based on your assigned system requirement, you may need to change the dp position by modifying the code here.
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module quad_seven_seg (
    input wire clk,
    input wire [3:0] val3, val2, val1, val0,  //4 BCD digits - each 4-bit
    output wire [3:0] an,  //4-bit anode control
    output reg [6:0] seg, //7-seg: abcdefg
    output wire dp
    );

    //Register Declarations
//    parameter max_count20 = 400_000; //400_000, Simulation = 4
    parameter max_count20 = 4; //400_000, Simulation = 4
    reg [19:0] cntr20 = 0;           // 20-bit counter to divide the 100MHz on board clock
    reg [1:0] step = 2'b00 ;      // step will determine the mux output
    reg en = 1'b0;                // en=1 will increment the step by 1
    reg [3:0] mux_out = 4'd0;     // mux_out will be any of the four val depending on step

  
    //20-bit counter with frequency of 100MHz divide by 400000 = 250 Hz, i.e. period is 4 ms
    //So that the human eye is able to view the seven segment correctly
    always@(posedge clk)
    begin
        if (cntr20 >= max_count20)
            cntr20 <= 20'd0;
        else
            cntr20 <= cntr20 + 1;
    end

    //Enable Signal Logic for 2 bit counter
    always @ (posedge clk) begin
         if (cntr20 == max_count20 - 1)
           en <= 1'b1;
         else
           en <= 1'b0;
     end
   

    //2 bit couter with enable
    always@(posedge clk)
        if(en) begin 
          step <= step + 1;
        end else begin
          step <= step;
    end  
   
    // 2 to 4 Encoder
    assign an[0] = !(step == 0);  //an0 is logic 0 when step is 00
    assign an[1] = !(step == 1);
    assign an[2] = !(step == 2);
    assign an[3] = !(step == 3);

    assign dp = !(step == 3);   //Default position. Might need to be changed according to specific system!!
    
    // 4 to 1 Multiplexer
    always@(*)
      case (step)       
          0: mux_out = val0;
          1: mux_out = val1;
          2: mux_out = val2;
          3: mux_out = val3;
          default: mux_out = 4'bzzzz;
      endcase
     
   
    // 4 to 7 Decoder
    // the seven segments are activel low
    always@(*)
      case (mux_out)     // abcdefg
        4'd0 :    seg = {7'b0000001}; //h01 - display 0
        4'd1 :    seg = {7'b1001111}; //h4F
        4'd2 :    seg = {7'b0010010}; //h12
        4'd3 :    seg = {7'b0000110}; //h06
        4'd4 :    seg = {7'b1001100}; //h4C
        4'd5 :    seg = {7'b0100100}; //h24
        4'd6 :    seg = {7'b0100000}; //h20
        4'd7 :    seg = {7'b0001111}; //h0F
        4'd8 :    seg = {7'b0000000}; //h00
        4'd9 :    seg = {7'b0000100}; //h04
        4'd10:    seg = {7'b1111110}; //hFE - display '-', used in refund state
        default : seg = {7'b1111111}; //hFF default: no display
      endcase
    
endmodule