I am using the ZCU102 Ultrascale+ board and have replaced the default DDR memory with 32 GB - DDR4 (row address bits: 17, dual rank, column bits: 10, Bank group: 2 bits, Bank Address: 2 bits). In order to access the 32 GB of memory, 36 logical address bits will be used and I am not sure how they will be mapped to the DRAM addressing!
UG 1087: Pg - 439:440 says that the ADDRMAP [0-11] registers acts as an intermediate mapper for HIF to DRAM addressing. Using the value of these registers in psu_init.c file, I am able to link the HIF address bits to DRAM addressing. On these pages, equation 17-1 returns HIF address bit number and the same expression returns AXI address bit number in equation 17-3 which seems conflicting! I am not sure how to connect the AXI logical and HIF addresses. In the case of logical addresses, the last three bits as a byte index and are always masked with 0's as mentioned in the above link on Xilinx forums.
On the other hand, https://www.xilinx.com/support/answers/71359.html says that the HIF[0] is the DRAM column bit 0. It also says that: To perform the mapping from the byte-addressable AXI to DRAM addressing, add three bits to the HIF ADDRMAP representation described above for 64-bit DQ. From this line, I think that shifting the HIF address left by 3 bits may help to relate it with the AXI byte address of 36 bits! But everything seems confusing to me at this moment.
My end goal is to decode the logical address say, 0x 8 BE00 7620 into DRAM addressing to identify which bits will be mapped to Row/Column/Bank/Bank Group/ Rank and so on.
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fpga_123
Hello,
I am using the ZCU102 Ultrascale+ board and have replaced the default DDR memory with 32 GB - DDR4 (row address bits: 17, dual rank, column bits: 10, Bank group: 2 bits, Bank Address: 2 bits). In order to access the 32 GB of memory, 36 logical address bits will be used and I am not sure how they will be mapped to the DRAM addressing!
Based on one thread in Xilinx forums, https://forums.xilinx.com/t5/Memory-Interfaces-and-NoC/How-to-map-the-AXI4-address-to-the-ddr4-memory-address/td-p/954407, for the requirement of BANK-ROW-COLUMN addressing, the AXI bytes could be mapped to the DRAM bits as Rank[34]_BankGroup[33:32]_Banks[31:30]_Row[29:13]_Column[12:3]_byteIndex[2:0]. But I am not sure if this is correct.
UG 1087: Pg - 439:440 says that the ADDRMAP [0-11] registers acts as an intermediate mapper for HIF to DRAM addressing. Using the value of these registers in psu_init.c file, I am able to link the HIF address bits to DRAM addressing. On these pages, equation 17-1 returns HIF address bit number and the same expression returns AXI address bit number in equation 17-3 which seems conflicting! I am not sure how to connect the AXI logical and HIF addresses. In the case of logical addresses, the last three bits as a byte index and are always masked with 0's as mentioned in the above link on Xilinx forums.
On the other hand, https://www.xilinx.com/support/answers/71359.html says that the HIF[0] is the DRAM column bit 0. It also says that: To perform the mapping from the byte-addressable AXI to DRAM addressing, add three bits to the HIF ADDRMAP representation described above for 64-bit DQ. From this line, I think that shifting the HIF address left by 3 bits may help to relate it with the AXI byte address of 36 bits! But everything seems confusing to me at this moment.
My end goal is to decode the logical address say, 0x 8 BE00 7620 into DRAM addressing to identify which bits will be mapped to Row/Column/Bank/Bank Group/ Rank and so on.
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