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joestoy

Configuring Axi Quad SPI block for Arty A7-100

Question

I'm trying to build a design for the Arty A7-100 (not using MicroBlaze), using the AXI Quad SPI memory for user data (and also for bitstream storage).  The Reference Manual (and the master .xdc file) mention six external pins for this (actually the .xdc file only mentions five).  But when I select the Arty A7100/External Memory/Quad SPI Flash from the "Board" window, it gives me a block for which the SPI_0 interface has 18 pins.  Essentially each data pin has become three (_i, _o and _t).  Am I supposed to put IO buffers there myself, or have I somehow got the wrong block?  If so, please would someone point me to the right package?  Thanks

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A careful reading of Xilinx's PG153 suggests that, depending on the configuration, only a few of the signals need be connected.  So I now think that actually it's OK.

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