SPI Memory Tester: IPI-BD and VHDL


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Hi to the community. I would like to mention that I have posted a FPGA design that memory byte tests the Pmod SF3 with 256Mbit N25Q flash chip.

You can find a link to this project at http://timothystotts.github.io/.

The name of the project is fpga-serial-mem-tester-1 .

The project sources contain some features beyond testing the QSPI flash chip.

Regards,

Tim S.

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Hi to the community. As with the SPI Accelerometer project, I created a top-level architecture diagram of this project, the Serial Flash Memory Tester. It could help a person decide if there are reusable modules for their own project.

Regards,

Tim S.

1091291666_SF-Tester-Design-Diagrams-Architecture1.thumb.png.6bc1397a208d971616f22e162c235621.png

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  • 2 weeks later...

Hi to the community. The GitHub repository now has a section for Lab Verification of the Pmod busses. SPI values are captured with Waveforms as digital logic analyzer to a Pmod TPH2. I authored a Python script that will translate Pmod CLS SPI bus activity and Pmod SF3 SPI bus activity (in separate files) into human-readable statements of the bus transfers.

The script:

https://github.com/timothystotts/fpga-serial-mem-tester-1/blob/master/Lab-Verification/display_pmod_parse_from_spi_spy.py

Example data inputs and outputs:

https://github.com/timothystotts/fpga-serial-mem-tester-1/tree/master/Lab-Verification/SF-Tester-Design-VHDL

Regards,

Tim S.

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