MuxSSD driver for the Pmod SSD

[Tim S.]

I authored a minimal Vivado IP design to control a single Pmod SSD with extension cable on a single jack of a FPGA board. The IP is called MuxSSD and allows writing either digit at any time with no need to use a fast GPIO trick in the application C code.

This driver is part of my previously mentioned Accelerometer Tester design.

The project is hosted at: https://github.com/timothystotts/fpga-serial-acl-tester-1 .

Tim S.

[Tim S.]

The software driver Makefile for this module was updated to work with Vitis 2020.2 .

See:

https://github.com/timothystotts/vivado-library/branches

branch

zybo-z7-20-vivado-2020.2

or

arty-a7-100-vivado-2020.2

 

Regards,

Tim S.

 

[Tim S.]

A refresh of the Accelerometer Tested design can be found at:

https://github.com/timothystotts/fpga-serial-acl-tester-3/

The design now supports the following development boards:

- Digilent Inc. Arty S7-25 FPGA development board containing a small Xilinx Spartan-7 FPGA

- Digilent Inc. Arty A7-100 FPGA development board containing a large Xilinx Artix-7 FPGA

- Digilent Inc. Zybo Z7-20 APSoC development board containing a moderate Zyng-7000 SoC.

The design includes equivalent examples in Block Design, Verilog-only, SystemVerilog-only, and VHDL-only.

The VHDL example includes a minimal OS-VVM test-bench example that can be adapted to run with GHDL on Linux.

Tim S.