Arty S7 Timer caputre

[Erick]

Hi,

I am trying to setup a timer capture on my Arty S7 board that measures the pulse width (high trigger) of an input signal and then access that value in SDK (Vitis) where I can send it out a UART.  I am having a bit of difficulty with this and was hoping someone could point me to some examples.  I am primarily using the block diagram design in Vivado.  Any help on this would be very much appreciated.
Thanks

[JColvin]

Hi @Erick,

I don't believe Digilent has any specific examples of this, but you can measure the pulse width in HDL (as illustrated in these two Xilinx threads here and here). You can then create your own IP core around this, either by following the formal Xilinx documentation for Vivado 2019.2 or through Digilent's older tutorial for a Zynq based board here.

Thanks,
JColvin