Packet data from TCP/IP core

[guynumber30]

hello, I was able to get communication with my nexys 4 between the computer over ethernet, I am able to send and receive packets and I can see what is happening over wire shark but I have no idea how I can redirect the data to logic and cut down the packet to the information I need. I had some theories as to hooking up a wire in parallel the RX line directly to logic but how would I be able to make sure the first packet is processed before the next one arrives? or am I suppose to be using a different line?  i had some theories on using the ethernet read active line in a multiplexer as the selector and sending data when its active but in not sure how successful this would be. any information would be helpful thank you. 

I have attached the module I converted the VHDL into a logic module and inserted it below. 

https://imgur.com/vZtB2FQ

and the ip core I am using is here 

 https://www.fpga-cores.com/tutorials/ethernet-on-nexys-4-ddr-artix-7-fpga-board/ 

thanks. 

 

[zygot]

32 minutes ago, guynumber30 said:

hello, I was able to get communication with my nexys 4 between the computer over ethernet

Nice!

33 minutes ago, guynumber30 said:

I have no idea how I can redirect the data to logic and cut down the packet to the information I need

Well, since everything is VHDL that shouldn't be too hard. Parsing incoming packets isn't complicated. So how to make progress?

First, I'd start with instantiating 2 ILAs. One is for Tx data and controls and is clocked by the Ethernet clock. The other is Rx data and controls and is clocked by the Ethernet PHY Rx clock. I'd start off by simply sending ARP packets at a periodic rate and capturing your FPGA board Rx and Tx packets. They are short packets. There are a number of ARP packet types but to start you want your PC to send a request ARP packet that your Arty will reply to. From there it's a matter of creating some code to parse incoming packets and write outgoing packets. Stick with simple point-point Ethernet and don't worry about fragmentation or out-of order packets to get started.

[guynumber30]

29 minutes ago, zygot said:

Nice!

Well, since everything is VHDL that shouldn't be too hard. Parsing incoming packets isn't complicated. So how to make progress?

First, I'd start with instantiating 2 ILAs. One is for Tx data and controls and is clocked by the Ethernet clock. The other is Rx data and controls and is clocked by the Ethernet PHY Rx clock. I'd start off by simply sending ARP packets at a periodic rate and capturing your FPGA board Rx and Tx packets. They are short packets. There are a number of ARP packet types but to start you want your PC to send a request ARP packet that your Arty will reply to. From there it's a matter of creating some code to parse incoming packets and write outgoing packets. Stick with simple point-point Ethernet and don't worry about fragmentation or out-of order packets to get started.

thanks! I will try this and get back to you, also thanks for your other posts I was reading through them in the forum.  

[PhDev]

What do you mean with 

Quote

 redirect the data to logic and cut down the packet to the information I need

Since you are using a FC1002 Ethernet core the TCP packet data will be streamed out to logic with an AXI stream. This stream is used by your logic.

The AXI stream signals are

TCP0_TxData, TCP0_TxValid, TCP0_TxReady for transmit data

and 

TCP0_RxData, TCP0_RxValid, TCP0_RxReady for receive data