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How to setup Xilinx MIPI D-PHY to decode Pcam 5C camera signals


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Hello,

I'm using a Zybo Z7-20 board together with the Pcam 5C camera module and I have a question regarding the MIPI D-PHY settings in the Zybo-Z7-20-pcam-5c project.
I want to replace the Digilent MIPI_D_PHY_RX with the Xilinx MIPI D-DPHY.

My issue is, that the Xilinx MIPI D-PHY does not output any AXI-Stream signals and that I see permanent 'Start-of-Transmission (SoT) Error' (errsoths = '1') reported on the output port of the Xilinx MIPI D-PHY. This error occurs, according to the Xilinx MIPI D-PHY datasheet, when the HS_SETTLE parameter is not matching. The standard HS_SETTLE parameter in the Xilinx MIPI D-PHY is 145ns. The DPHY_LaneSFEN.vhd file, which is part of the Digilent MIPI D-PHY, uses a constant named 'kTHSSettle' which is set to 85ns.

Even if I setup the Xilinx MIPI D-PHY to use a HS_SETTLE time of 85ns, I still see the 'Start-of-Transmission Error' reported by the Xilinx MIPI D-PHY.

The camera setup is done by the Digilent pcam_vdma_hdmi application which configures the camera to run in the standard 1080p30 setup mode (2-MIPI lanes, with 420 Mbps/lane).
 
What are the settings for the Xilinx MIPI D-PHY to decode the 2-lane MIPI signal received from the PCAM 5c camera board?

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You are on the right track. The settings that control the timing of the low-power high-speed transition need to match between the transmitter and receiver. It is easier if you scope it, triggering on an LP-10 state and measuring the time it takes for the sensor to switch to high-speed.

The following registers control the camera timing:

		//MIPI timing
		// [5]=0 T_LPX global timing select=auto pclk2x
		{0x4805, 0x10},//Default=0x10
		//T_HS_ZERO = MIN HS ZERO + T_UI*MIN HS ZERO_UI
		//MIN HS ZERO H (ns)
		{0x4818, 0x00},//Default=0x00
		//MIN HS ZERO L (ns)
		{0x4819, 0xFF},//Default=0x96
		//MIN HS ZERO_UI
		{0x482A, 0x05},//Default=0x05

		//T_HS_PREPARE = MIN HS PREPARE + T_UI*MIN HS PREPARE_UI
		//MIN HS PREPARE H (ns)
      {0x4826, 0x00},//Default=0x00
      //MIN HS PREPARE L (ns)
      {0x4827, 0x32},//Default=0x32
      //MIN HS PREPARE_UI
      {0x4831, 0x04},//Default=0x04

We will get to publishing a Xilinx MIPI IP demo project eventually.

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Thanks for your reply.

I’m using the OV5640 initialization which can be found here: https://github.com/Digilent/Zybo-Z7-20-pcam-5c/blob/master/sdk/appsrc/pcam_vdma_hdmi/ov5640/OV5640.h
In this file the HS_ZERO and HS_PREPARE camera register values are not defined. They stay on their default value, mentioned in the camera datasheet:

T_UI = 24 ns (Register value 0x4837)

T_HS_ZERO    = MIN_HS_ZERO    + T_UI*MIN_HS_ZERO_UI    = 0x96 ns + 24 ns * 0x05 = 150 ns + 120 ns = 270 ns
T_HS_PREPARE = MIN_HS_PREPARE + T_UI*MIN_HS_PREPARE_UI = 0x32 ns + 24 ns * 0x04 =  50 ns +  96 ns = 146 ns

HS_SETTLE = T_HS_ZERO + T_HS_PREPARE = 416 ns

This is way higher than the kTClkSettle time constant which defines probably the HS_SETTLE in the Digilent MIPI D-PHY.

How did Digilent figure out the correct HS_SETTLE time? Only by measuring?

Without having a scope to measure, what’s the actual value to use for the HS_SETTLE time?

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Frustratingly, I could never find the equation that worked consistently across resolutions for the HS values the camera uses. The sensor datasheet is not exactly verbose on the matter. Xilinx MIPI DPHY IP support is expected together with UltraScale+ support in a month or so. You can try setting a large value in the sensor for HS_ZERO, and try increasing HS_SETTLE in D-PHY Rx until it works.

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Like you said, there's no specific explanation for the HS_ZERO and HS_PREPARE registers in the camera datasheet.
I don't know the ranges of HS_ZERO and HS_PREPARE that are accepted by the camera. That's why I try to avoid making changes there.

I did some simple tests on the Xilinx MIPI D-PHY and programmed an automatic sweep from low to high HS_SETTLE values.
Unfortunately I couldn't find a correct HS_SETTLE value. All of the values tested caused D-PHY errors.

There's a petalinux project for the Zybo Z7-20 board which contains Xilinx modules for MIPI decoding and signal processing.
The Xilinx MIPI RX module is configured for 2-lanes, 800 Mbps and YUV422. I guess this project was designed to work with the OV5640 sensor, right?

Maybe I find there some settings on how to setup the camera or Xilinx MIPI D-PHY.

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