I´m trying to implement a FIR filter with a sampling rate of 16 kHz on the Genesys 2 Board (Vivado 2019.2, VHDL). For that reason I need to configure the onboard Audio-Codec (ADAU1761). I already designed a FIR-filter, that I want to use later. Unfortunately I am quite new to FPGA design and I´m struggling a bit with it.
I converted this framework into a Genesys 2 framework, since it is the same Audio Codec. Unfortunately something is not working and I don´t know how to go on right now.
At first I want to give the LINE IN input directly to the HP OUT Output. As a next step I want to integrate my previous FIR filter. For evaluation of proper functionality of the FIR filter I´m going to use the Analog Discovery 2 (analyzing the transfer function with sinus sweeps).
My next steps:
I wanted to use the ILA (Integrated Logic Analyzer) for the signal values. Unfortunately I have some problems when integrating the ILA for line_in_ and hphone_out_ signals (Error: OBUFT [DRC REQP-1581] obuf loaded: OBUFT_i i_audio/…/OBUFT_inst pin O drives one or more invalid loads. The loads are: i_audio/…/i2c_data[0]_i_1
Moreover I wanted to use the AD2 as logic analyzer and therfore route the signals on some pins (I´m waiting for bread board cables).
Furthermore when generating the bitsteam I get critical warnings:
[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
[Board 49-67] The board_part definition was not found for digilentinc.com:genesys2:part0:1.1. This can happen sometimes when you use custom board part. You can resolve this issue by setting 'board.repoPaths' parameter, pointing to the location of custom board files. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command.
I first thought my framework is working but when setting hphone_out_l and hphone_out_r to 0, I still hear the music from my IPod (because of the default startup program).
When finished, I want to upload the Audio Codec Interface. Maybe someone else also needs the interface.
If someone can help me or has another Audio Codec design for the Genesys 2 (that he is willing to share), I would be very pleased!
I added an Overview of the modules, a block design for all modules, the previous codec configuration (docx) and the code modules. If desired I can upload additional files.
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itse me mario
Hello everybody,
I´m trying to implement a FIR filter with a sampling rate of 16 kHz on the Genesys 2 Board (Vivado 2019.2, VHDL). For that reason I need to configure the onboard Audio-Codec (ADAU1761). I already designed a FIR-filter, that I want to use later. Unfortunately I am quite new to FPGA design and I´m struggling a bit with it.
I found an article „Audio Interface for the Zedboard“ from Stefan Scholl (TU Kaiserslautern Germany, see https://kluedo.ub.uni-kl.de/frontdoor/deliver/index/docId/4034/file/zedboard_audio_doc.pdf), which is based on a framework from Mike Field alias hamster). Also the VHDL-files are included (see https://github.com/ems-kl/zedboard_audio).
I converted this framework into a Genesys 2 framework, since it is the same Audio Codec. Unfortunately something is not working and I don´t know how to go on right now.
At first I want to give the LINE IN input directly to the HP OUT Output. As a next step I want to integrate my previous FIR filter. For evaluation of proper functionality of the FIR filter I´m going to use the Analog Discovery 2 (analyzing the transfer function with sinus sweeps).
My next steps:
Furthermore when generating the bitsteam I get critical warnings:
[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
[Board 49-67] The board_part definition was not found for digilentinc.com:genesys2:part0:1.1. This can happen sometimes when you use custom board part. You can resolve this issue by setting 'board.repoPaths' parameter, pointing to the location of custom board files. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command.
I first thought my framework is working but when setting hphone_out_l and hphone_out_r to 0, I still hear the music from my IPod (because of the default startup program).
When finished, I want to upload the Audio Codec Interface. Maybe someone else also needs the interface.
If someone can help me or has another Audio Codec design for the Genesys 2 (that he is willing to share), I would be very pleased!
I added an Overview of the modules, a block design for all modules, the previous codec configuration (docx) and the code modules. If desired I can upload additional files.
I´m looking forward to hearing from you.
Thanks a lot and stay healthy,
Mario
Registersettings.docx OverviewAndModules_new.pdf Genesys2Master.xdc adau1761_configuraiton_data.vhd ADAU1761_interface.vhd ADAU1761_izedboard.vhd audio_testbench.vhd audio_top.vhd clocking.vhd i2c.vhd i2s_data_interface.vhd i3c2.vhd reg_pack.vhd
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