Using Verilog Modules in Vitis

[Erick]

Hello,

I am sure this is an extremely noob question but I am just getting started with FPGAs...

I created a simple ROM module in Verilog (2 bit address "addr" and 8 bit data output "data")

I have also created a block design microblaze project with a uart that I have been able to send things out of in the past.  My question would be how do I access the ROM using Vitis?  I would like to send the data in each ROM address out of the UART, but I am not understanding how to do this in Vitis.

Thanks for any help.

[artvvb]

Hi @Erick

In order for the processor to be able to read data from a module, the module needs to have a memory mapped interface connected to the processor, so that the processor can read or write register data through the addresses that have been assigned to the module's interface. For microblaze, this would (usually) be an AXI interface. This guide should be able to get you started, but is fairly out-of-date, and only handles data written from a processor to an IP. Fair warning, this is a pretty broad topic, and you can find plenty of posts on this forum, and elsewhere on the web, about designing AXI IP, and the common pitfalls you may run into.

Thanks,

Arthur