USB PROG/UART schematic request

[adelcastillo@spacevector.c]

To Whom it may concern:

 

  Can you please provide the USB PROG/UART schematic (page 10 of documented schematics) for the Arty A7 board?

Thanks
Art

[JColvin]

Hi @adelcastillo@spacevector.c,

I apologize for the delay. Digilent does not typically provide this schematic.

Thanks,
JColvin

[adelcastillo@spacevector.c]

Hi JColvin!

  Is it possible to establish an NDA to get a copy of this?

Thanks
Art

[JColvin]

Hi @adelcastillo@spacevector.c,

Potentially, yes. I don't personally know the full details behind the NDA, but I do know that we offer a licensing option. I have sent you a DM with the appropriate Digilent contact who will be able to provide you more details on this.

Thanks,
JColvin

[JerryG]

Ah, yes, the infamous "This page intentionally left blank." page in the Arty schematic...

This page is the interface between the FTDI chip used to implement the Jtag interface to the Artix FPGA. I'm not sure exactly what Digilent is trying to protect here as the schematic is pretty straightforward (I have a schematic for this section of the board. I didn't get it from Digilent--I beeped it out from a dead Arty board and drew the schematic myself).

Please don't ask me for a copy--If Digilent doesn't want to give this info out, they must have their reasons and I'll respect that by not distributing my version.

[zygot]

Intellectual Property is in the eye of the beholder. I'm inclined to agree with @JerryGthat there's nothing to see here folks... but only Digilent can make the decision of whether or not the missing schematic page has a value in bad will, that is exceeded by whatever information is being withheld by a schematic page.

I once worked for a small company that was owned by a very large international conglomerate. Boy did they love patents. The fact that all of the patent ideas that I saw didn't work, weren't part of any actual product,  or was simply a bad idea or not defensible if challenged in court doesn't matter. Patents are playthings of lawyers who generally can't or don't bother to assess their worthiness. They make the same money on both ends of patent fights. If your company has 10000 patents and you get into a fight with another company with only 1000 patents you might be able to use them to make your opponent blink... if you are a good poker player... but in general civil law is won by whoever can give lawyers the most money.  

[anshumantech]

USB Prog USRT page is intentionally kept blank in circuit schematics provided by you for Arty A7-35T/100T board. Why?Is that something to do with you tying to protect some minor IP?

In Arty A7 reference manual you have mentioned J8 and J10 as parts concerning programming/JTAG? Can we use HS1 or HS3 Modules for USB to JTAG programming?

Will HS1 or HS3 JTAG modules enable Logic analyzer mode of web pack? 

Edited September 3, 2020 by anshumantech

[JColvin]

Hi @anshumantech,

Yes, you should be able to use the Digilent JTAG modules and use the Integrated Logic Analyzer in Vivado. The JTAG HS1 and JTAG HS2 should be able to connect directly (via a 6-pin connector) to the JTAG connector between the JB and JC Pmod ports. The JTAG HS3 can also connect through the same port though you'll need to individually wire the appropriate signals to the Arty A7.

Thanks,
JColvin

[anshumantech]

Thanks, for precise reply.

Then question is what are you trying to hide on USB PORG UART page? Have they laid out HS1/HS3 circuit on that page? Is there any link setting to use either J8 port(HS1/HS3) or converter circuit on USB PROG UART page; something like 4 pole multiplexer? Typically FPGA has only one JTAG port.

[JerryG]

On 9/2/2020 at 12:08 AM, anshumantech said:

USB Prog USRT page is intentionally kept blank in circuit schematics provided by you for Arty A7-35T/100T board. Why?Is that something to do with you tying to protect some minor IP?

I can only surmise they do this as a result of an NDA with another party, or something similar, because I've reverse engineered the circuit on that part of the board and drawn the schematic and there's nothing special there at all--it's pretty much a bog standard implementation of what FTDI publishes on their site.

[anshumantech]

@JerryG

Thanks, based on your efforts you may tell whether they have used FT232H IC?

[JColvin]

Hi @anshumantech,

It is using a FT2232HQ as per the Arty A7 Reference Manual: https://reference.digilentinc.com/reference/programmable-logic/arty-a7/reference-manual#usb-uart_bridge_serial_port.

Thanks,
JColvin

[anshumantech]

Page 10 which is kept blank, in Arty 7 board schematics, has USB port (J10) to USB controller patented design. The output pins from it appear at J8 JTAG port. Therefore how can we use external JTAG HS2/HS3 type module at J8 as its output will be shorting to similar pins from USB controller IC (FT2232H) connected to J10? or resistors like R145, R147 prevent them shorting each other.

[JColvin]

Hi @anshumantech,

Steps were taken to prevent any cross signal problems. I've also tested this with a JTAG HS3 individually wired to J8 while also having a USB cable directly connected to the USB-UART port, and the Vivado software (as well as Digilent's Adept software) will only allow a single connection to the FPGA at a time.

Thanks,
JColvin

[anshumantech]

Thanks but I am curious to know about how are these cross signal issues resolved as Fig 4.1 in Arty reference manual shows direct connection of J8 and USB converter at J10. Please specify how?

[malexander]

@anshumantech

If you look at the top left corner of sheet 6 you will find header J8 attached to the TMS, TDI_FPGA, TCK, and TDO_FPGA nets through resistors R163, R164, R165, and R166. Those resistors are present to help prevent damage from any drive conflicts that may occur when both an external and onboard programmer are active. However, JTAG programming can't function correctly when both an onboard and external programmer are active. There are tri-state buffers between the onboard USB controller and the TMS, TDI_FPGA, and TCK nets. These buffers are held in tri-state when the programmer isn't open in Adept or Vivado/Vitis. The tri-state buffers are what allows you to use an external programmer with J8 (JTAG-HS1 or JTAG-HS2 recommended for 6-pin header) - just be sure that you haven't opened the onboard interface in Adept or Vivado/Vitis.

Thanks,
Michael

[anshumantech]

Artix7-35T and 100T both have same package CSG324. Can we solder either 35T or 100T IC on same footprint depending on application requirement?

[xc6lx45]

OT but yes I think that is generally the idea. Usually you scale devices down (start with a big one for faster build cycle, ILA etc). Then squeeze the design into the smallest device possible in volume production.

If you scale up, it obviously puts more stress on DC / thermal design.

[Endres]

Sorry for pushing but I would also like to have the schematic, however for Basys 3. This would save a lot of useless reversing work (involving to salvage one board) for a schematic that seems to be almost the same as in the FT2232 datasheet or similar.

Can you please elaborate on why this part is left out of the schematics?

[JColvin]

Hi @Endres,

I can't imagine this will be a satisfactory answer, but essentially the appropriate powers that be decided that Digilent will not release the programming portion of the schematic for any of our boards. If you have a particular question, we might be able to answer it, but I'm not going to be able to make any promises on that.

It might be possible to be able to get an NDA agreement regarding our programming solution, but I have personally never heard of this being granted during my time at Digilent.

Thanks,
JColvin

[malexander]

@Endres Having access to the schematic will help you replicate the circuitry but it won't allow Vivado / Vitis to see the device. For that, the device must be programmed with a special configuration, which we consider IP that we may license to third parties.

[zygot]

2 hours ago, malexander said:

Having access to the schematic will help you replicate the circuitry but it won't allow Vivado / Vitis to see the device. For that, the device must be programmed with a special configuration, which we consider IP that we may license to third parties.

Gee... sometimes trying to explain things just makes the situation more confusing. So... what you're saying is that there isn't any good reason for all of those missing schematic pages for your hardware because the schematic doesn't have anything to do with Digilent's Intellectual Property given that the configuration information has never been part of the schematics?

 

Edited May 26, 2022 by zygot

[malexander]

1 hour ago, zygot said:

Gee... sometimes trying to explain things just makes the situation more confusing. So... what you're saying is that there isn't any good reason for all of those missing schematic pages for your hardware because the schematic doesn't have anything to do with Digilent's Intellectual Property given that the configuration information has never been part of the schematics?

 

I'm not trying to cause confusion, but rather point out that having the missing page may not allow Endres to achieve the desired goal. Not publishing portions of some schematics, or in the other cases withholding entire schematics, is a business decision. Individuals that want access to missing pages or schematics can request them and in some cases Digilent may provide unpublished pages or schematics.

[zygot]

Wasn't suggesting any intent of causing confusion. No doubt many of your readers will be more frustrated though than they were before you posted the new insight.

Properly managing potentially income producing company IP is not just a business decision but a fiduciary responsibility. Business decisions do have both positive and negative consequences so one would hope that there's a good rational for publishing blank pages in product schematics, as this is a sure way to cause consternation for customers. I'm doubtful that a policy of providing hidden information to some customers without a clearly published guideline lessens the negative energy.

When Digilent boards used the Cypress USB solution there were no blank pages on Digilent schematics, even though the functionality was the same as it is for the FTDI solution. Personally, I haven't found the missing information to have affected any of the many projects that I've done using Digilent FPGA platforms.

For anyone wanting to design their own FPGA board with the ability to allow the tools to access the JTAG chain seamlessly, as Digilent has done for a long time, there are certainly plenty of options available that doesn't involve cloning schematics. Edited May 27, 2022 by zygot

[DmDerev]

In my humble opinion, the board intended for makers and coming from what sometime ago was a reputable company should come with complete and accurate schematics. If it is ("surprise") missing, it does not improve the reputation, it actually says that the users may have more troubles in troubleshooting if a problem happens. I did not pay attention to a missing page before I tried to create a top level Verilog file for my design and needed to check what is the direction of UART_TX_IN and UART_RX_OUT? Are they "in" and "out" from UART of FPGA view? These signals are always confusing because there is no standard notation there. I searched the schematics to find that these signals do not go anywhere, and it was the reason to say s*... 

I do not take the arguments about "IP" below. For majority of customers, the only reason to buy Digilent boards is to avoid headache of building custom boards which does not justify effort in low volumes. For such customers Digilent creates unjustified additional difficulties and diminishes the value of buying from Digilent.

[DmDerev]

P.S. The "secret" is explained in detail by Xilinx in Appendix E of User Guide UG908: 

https://docs.xilinx.com/r/en-US/ug908-vivado-programming-debugging/JTAG-Cables-and-Devices-Supported-by-hw_server

For FTDI devices to be recognized as a USB-to-JTAG interface in Xilinx® JTAG software tools such as XSDB or the Vivado® Hardware Manger the EEPROM on the FTDI device must be programmed with a custom firmware provided by Xilinx. Programming the FTDI is accomplished by using the program_ftdi utility included in the Vivado install as a Tcl command. Once programmed, the FTDI device will be recognized as a valid programming cable in Vivado.

Note: For on-board implementation details including FTDI connectivity, please reference the Xilinx VCK190 Schematics available in XTP610 on https://www.xilinx.com/products/boards-and-kits/vck190.html.

The program_ftdi utility supports the following FTDI devices: • FT232H • FT2232H • FT4232H

The "program_ftdi" utility may be used to read out configuration information from the board/cable.  When used with read, the command reads back the content of FTDI EEPROM to standard out. if -fileout option is used, the read back information is written to the file specified.

The connection is using ABUS0..ABUS6 for JTAG signals, sensing the power and resetting the board. The pin assignment for JTAG interface and the descriptions of the signals are shown in Table 3.7 of FT2232H and FT4232H datasheet.

Again, it is a shame that the board intended to help Xilinx in selling their products attempts to confuse users by hiding the information.