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USB PROG/UART schematic request


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Hi @[email protected],

Potentially, yes. I don't personally know the full details behind the NDA, but I do know that we offer a licensing option. I have sent you a DM with the appropriate Digilent contact who will be able to provide you more details on this.

Thanks,
JColvin

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Ah, yes, the infamous "This page intentionally left blank." page in the Arty schematic...

This page is the interface between the FTDI chip used to implement the Jtag interface to the Artix FPGA. I'm not sure exactly what Digilent is trying to protect here as the schematic is pretty straightforward (I have a schematic for this section of the board. I didn't get it from Digilent--I beeped it out from a dead Arty board and drew the schematic myself).

Please don't ask me for a copy--If Digilent doesn't want to give this info out, they must have their reasons and I'll respect that by not distributing my version.

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Intellectual Property is in the eye of the beholder. I'm inclined to agree with @JerryGthat there's nothing to see here folks... but only Digilent can make the decision of whether or not the missing schematic page has a value in bad will, that is exceeded by whatever information is being withheld by a schematic page.

I once worked for a small company that was owned by a very large international conglomerate. Boy did they love patents. The fact that all of the patent ideas that I saw didn't work, weren't part of any actual product,  or was simply a bad idea or not defensible if challenged in court doesn't matter. Patents are playthings of lawyers who generally can't or don't bother to assess their worthiness. They make the same money on both ends of patent fights. If your company has 10000 patents and you get into a fight with another company with only 1000 patents you might be able to use them to make your opponent blink... if you are a good poker player... but in general civil law is won by whoever can give lawyers the most money.  

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USB Prog USRT page is intentionally kept blank in circuit schematics provided by you for Arty A7-35T/100T board. Why?Is that something to do with you tying to protect some minor IP?

In Arty A7 reference manual you have mentioned J8 and J10 as parts concerning programming/JTAG? Can we use HS1 or HS3 Modules for USB to JTAG programming?

Will HS1 or HS3 JTAG modules enable Logic analyzer mode of web pack? 

Edited by anshumantech
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Hi @anshumantech,

Yes, you should be able to use the Digilent JTAG modules and use the Integrated Logic Analyzer in Vivado. The JTAG HS1 and JTAG HS2 should be able to connect directly (via a 6-pin connector) to the JTAG connector between the JB and JC Pmod ports. The JTAG HS3 can also connect through the same port though you'll need to individually wire the appropriate signals to the Arty A7.

Thanks,
JColvin

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Thanks, for precise reply.

Then question is what are you trying to hide on USB PORG UART page? Have they laid out HS1/HS3 circuit on that page? Is there any link setting to use either J8 port(HS1/HS3) or converter circuit on USB PROG UART page; something like 4 pole multiplexer? Typically FPGA has only one JTAG port.

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On 9/2/2020 at 12:08 AM, anshumantech said:

USB Prog USRT page is intentionally kept blank in circuit schematics provided by you for Arty A7-35T/100T board. Why?Is that something to do with you tying to protect some minor IP?

I can only surmise they do this as a result of an NDA with another party, or something similar, because I've reverse engineered the circuit on that part of the board and drawn the schematic and there's nothing special there at all--it's pretty much a bog standard implementation of what FTDI publishes on their site.

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Page 10 which is kept blank, in Arty 7 board schematics, has USB port (J10) to USB controller patented design. The output pins from it appear at J8 JTAG port. Therefore how can we use external JTAG HS2/HS3 type module at J8 as its output will be shorting to similar pins from USB controller IC (FT2232H) connected to J10? or resistors like R145, R147 prevent them shorting each other.

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Hi @anshumantech,

Steps were taken to prevent any cross signal problems. I've also tested this with a JTAG HS3 individually wired to J8 while also having a USB cable directly connected to the USB-UART port, and the Vivado software (as well as Digilent's Adept software) will only allow a single connection to the FPGA at a time.

Thanks,
JColvin

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@anshumantech

If you look at the top left corner of sheet 6 you will find header J8 attached to the TMS, TDI_FPGA, TCK, and TDO_FPGA nets through resistors R163, R164, R165, and R166. Those resistors are present to help prevent damage from any drive conflicts that may occur when both an external and onboard programmer are active. However, JTAG programming can't function correctly when both an onboard and external programmer are active. There are tri-state buffers between the onboard USB controller and the TMS, TDI_FPGA, and TCK nets. These buffers are held in tri-state when the programmer isn't open in Adept or Vivado/Vitis. The tri-state buffers are what allows you to use an external programmer with J8 (JTAG-HS1 or JTAG-HS2 recommended for 6-pin header) - just be sure that you haven't opened the onboard interface in Adept or Vivado/Vitis.

Thanks,
Michael

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OT but yes I think that is generally the idea. Usually you scale devices down (start with a big one for faster build cycle, ILA etc). Then squeeze the design into the smallest device possible in volume production.

If you scale up, it obviously puts more stress on DC / thermal design.

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