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linasr

Pcam Visible Border Line

Question

Dear All,

I was able to port the camera design to Genesys 2 board. I see this Visible Border Line as mentioned in Zybo Z7 demo description. Is there a solution for this problem already available? I use following IP blocks:

MIPI_D_PHY_RX (1.3) -> MIPI CSI-2 Receiver (1.1) -> AXI_BayerToRGB (1.0) -> AXI_GammaCorrection_0 (1.0) -> axi_vdma

Thank you

Linas

IMG_7183.jpg

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4 answers to this question

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You can try editing the AXI_BayerToRGB or replacing it with Xilinx's demosaic IP. You can try interpolation with duplicated margin, for example. You are on your own.

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