linasr Posted July 7, 2020 Share Posted July 7, 2020 Dear All, I was able to port the camera design to Genesys 2 board. I see this Visible Border Line as mentioned in Zybo Z7 demo description. Is there a solution for this problem already available? I use following IP blocks: MIPI_D_PHY_RX (1.3) -> MIPI CSI-2 Receiver (1.1) -> AXI_BayerToRGB (1.0) -> AXI_GammaCorrection_0 (1.0) -> axi_vdma Thank you Linas Link to comment Share on other sites More sharing options...
elodg Posted July 8, 2020 Share Posted July 8, 2020 https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-z7-pcam-5c-demo/start#visible_border_line Link to comment Share on other sites More sharing options...
linasr Posted July 8, 2020 Author Share Posted July 8, 2020 1 minute ago, elodg said: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-z7-pcam-5c-demo/start#visible_border_line This means no solution at the moment? Right? Can I help fixing this? Link to comment Share on other sites More sharing options...
elodg Posted July 8, 2020 Share Posted July 8, 2020 You can try editing the AXI_BayerToRGB or replacing it with Xilinx's demosaic IP. You can try interpolation with duplicated margin, for example. You are on your own. Link to comment Share on other sites More sharing options...
linasr Posted July 8, 2020 Author Share Posted July 8, 2020 Thank you Link to comment Share on other sites More sharing options...
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linasr
Dear All,
I was able to port the camera design to Genesys 2 board. I see this Visible Border Line as mentioned in Zybo Z7 demo description. Is there a solution for this problem already available? I use following IP blocks:
MIPI_D_PHY_RX (1.3) -> MIPI CSI-2 Receiver (1.1) -> AXI_BayerToRGB (1.0) -> AXI_GammaCorrection_0 (1.0) -> axi_vdma
Thank you
Linas
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