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Steven Cornett

Vivado ZMod ADC IP Not Compatible with Genesys ZU

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I attempted to load the ZMod ADC1410 A/D converter for the Genesys ZU3 board IP into my Vivado design (2019.2).  However, the ADC1410 controller cannot be loaded into Vivado 2019.2 because the IP does not support the Genesys board.

As a result, I have a AXI interface board for a board IP that won't load. 

Is there an update to the Vivado IP so that the AD board will work on Genesys ZU3?

 

Vivado-Gen_Zmod_ADC1410.png

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Posted (edited)

While you're waiting for that to happen you might consider alternatives. You can use the low level controller (not AXI controller ) and use an AXI stream interface to get samples into the board DDR memory. I've use the AXI Virtual  FIFO on the Eclypse-Z7 though that IP is limited to 256 KB per channel. I haven't tried finding out what impact multi-channel presents. You can easily aggregate the two ADC channels into a wide bus and use 1 Virtual FIFO channel. My sense is that with the Eclypse-Z7 and the Genesys-ZU boards Digilent got in a bit over their heads... just a opinion. You can wait or forge ahead on your own. For the Eclypse I've made the determination that waiting isn't a good strategy.

Edited by zygot

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If you look at the picture I showed, you'll see that I was able to get the AXI controller for the ZMod A/D card.  

It's precisely the Low Level Controller that was not compatible with the Genesys ZU board.  What would be the best path forward to make it compatible?

Sorry if I made that point unclear.

Steven P. Cornett

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Posted (edited)
24 minutes ago, Steven Cornett said:

It's precisely the Low Level Controller that was not compatible with the Genesys ZU board.

Well, that's odd because the low level controllers for both of Digilent's ZMODs are just HDL and don't use any Xilinx IP. I've used them both for HDL only designs, and for boards with a different FPGA device than the one that Digilent's Zmod support was written for. Both of the low level controllers require no additional coding to configure the ADC or DAC devices to be functional out of reset; that is they automatically configure them using the devices' SPI control interface. I can't imagine why you think that either would be incompatible with any particular FPGA board having a SYZYGY interface on it.

Of course I didn't use Digilent's IP in its packaged form using the board design flow. I did what I suggested as an alternate way of using the ZMODs in a design.

Edited by zygot

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Posted (edited)

I've found that recent versions of Vivado 'lock' Xilinx IP that was created for a part that is different than the one you might be using for a different project. You just have to 'upgrade' it to force a regeneration of the IP so that it targets the correct FPGA device. This is nothing more than poor error messaging. Packaging your IP introduces more opportunities for problems. That's how the board design flow works by design.

Edited by zygot

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20 hours ago, zygot said:

I've found that recent versions of Vivado 'lock' Xilinx IP that was created for a part that is different than the one you might be using for a different project. You just have to 'upgrade' it to force a regeneration of the IP so that it targets the correct FPGA device. This is nothing more than poor error messaging. Packaging your IP introduces more opportunities for problems. That's how the board design flow works by design.

Is that upgrade within the families supported in the component.xml file, where you add this line:

   <xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>

In the new file?

Do I then repackage the IP and regenerate it?

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Posted (edited)

@Steven Cornett,

I think that we're talking about two different things. I've used the ZMOD low level controller source code VHDL files to target an Artix A75T. Even though the PL of the ZYNQ 7000 series is roughly equivalent to the A75T they are not even in the same family as far as Vivado is concerned. I think that I confused you by being incomplete with my reply. In a few projects, I was actually porting one project from an Eclypse-Z7 target to an XEM7320 target and have a few BRAM and ROM Xilinx IP sources. When I imported them into the new project I saw that they were locked. I simply had Vivado 'upgrade' them. All of this was, for both projects, outside the board design flow. As far as the ZMOD code is concerned I just added the VHDL files as source since I wasn;t using any of the AXI higher level IP from Digilent.

I really don't know use the board design flow that much and can't offer advice on how to get around it's peculiarities.

Edited by zygot

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In other words you did your upgrades using make command from within Linux.  

From that it sounds like we wasted our money putting an instance in Windows since you need to go to bash to do anything useful when you hit even the slightest roadblock.

It sounds to me like you to do a "create and package IP" from within Vivado to upgrade the IP, is that correct?  In that case, I should then be able to rename and then select the new package, and have it work.

Does that sound reasonable?

 

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Actually, I just did it within the library by explicitly adding the Zynqultra family to the list of compatible devices and upgraded it that way.  

I am able to get it now, and I'll see if it works.

Maybe Vivado isn't as bad as I think it is.

Steven P. Cornett

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Just now, Steven Cornett said:

n other words you did your upgrades using make command from within Linux.  

No, no,

I've still not made my point clearly. This has nothing to do with Linux or Bash. Also, I'm not a representative of Digilent and I've never published any Xilinx IP that I've created and packaged.

If you go to the Digilent Project Vault you can see two of the projects that I'm referring to under the titles of 'Fun with Phasors'. The older one targets the Eclypse-Z7 and the more recent one the XEM7320. Both use the same sources, except that the XEM7320 isn't ZYNQ based so there was no board desoign flow or ZYNQ Processor block. Even for the Eclypse-Z7 version I didn't use the ZMOD AXI controller; in fact I didn't instantiate any Digilent IP the board design schematic at all. It's explained in the project documentation readme file.

By alternative design, I really mean alternative. Instead of trying to use the Digilent ZMOD IP by adding it to your board design create a minimal board design for your ZYNQ and add IP to the board design that lets you connect the ZMOD to the PS without using AXI IP at all. For this case I use BRAMs. 

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Posted (edited)
4 minutes ago, Steven Cornett said:

Actually, I just did it within the library by explicitly adding the Zynqultra family to the list of compatible devices and upgraded it that way.

Well, that was imaginative. Nice! I hope that this works out for you. Let us all know if you get the design working on the Genesys ZU so that I can keep that trick in mind.

Edited by zygot

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5 hours ago, zygot said:

Well, that was imaginative. Nice! I hope that this works out for you. Let us all know if you get the design working on the Genesys ZU so that I can keep that trick in mind.

Well, once I read through the documentation on the lower level part, that cleared up at least two other apparent blockages to progress, which is good.

That said, is there a tutorial for making a project with the ZMods?  I am unsure about how this is supposed to connect to the ZMod connector I physically placed the ADC1410 on, because unlike the PMODs, the ZMod does not seem to be listed on the board listing.

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Posted (edited)

Digilent provides documentation for replicating the demos but they have errors. It took me quite some time to figure it all out.

A good reason to replicate the demos is to get a good idea of how things are organized and hwo everything works.

As far as the XmodADC1410 goes, once I realized that Digilent's code only supports acquiring a maximum of 16383 samples, and after all of the pain and work trying to use the GIt repos I decide that Digilent's Eclypse-Z7 support isn't worth the effort for my own projects. I did figure out how to push 128K samples per channel into the PS DDR but 1 ms isn't good enough for most of the things that I want to do. Hence, I figured out an alternate plan using a different platform.

There are still application for which the Eclypse-Z7 hardware is adequate but it's just a lot easier to develop on a non-ZYNQ platform for now. I'm still hoping that Digilent will get things in order so that ZYNQ based platforms are worth developing applications on. For now it's too complicated and limited. Things might be better for using the ZmodDAC1411.

32 minutes ago, Steven Cornett said:

ZMod does not seem to be listed on the board listing.

Not sure what you mean by this. The most recent Digilent vivado-library repo has ZMOD support. Digilent's branched Git is a mess to navigate through if you don't know exactly what branch it is that you need. How you use the vivado-library IP to create a custom project is a mystery that I haven't ventured into. I have my own development path that's working for me.

One other problem that you will likely encounter is pin location constraints.  For the Eclypse-Z7 ADC/DAC demo branch support is only provided when you place the ADc and DAC pods onto a specific ZMOD port. Your board only has one ZMOD port but my guess is that Digilent doesn't have the constraints for your board... though perhaps they do in another branch of the repo.

Edited by zygot

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On ‎7‎/‎7‎/‎2020 at 2:58 PM, zygot said:

One other problem that you will likely encounter is pin location constraints.  For the Eclypse-Z7 ADC/DAC demo branch support is only provided when you place the ADc and DAC pods onto a specific ZMOD port. Your board only has one ZMOD port but my guess is that Digilent doesn't have the constraints for your board... though perhaps they do in another branch of the repo.

Does Digilent have the constraints for the ZMod on the Genesys, or is that something I'll have to track down as well?

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Posted (edited)

I should add that, as they sprinkle ZMOD goodness about on new platforms. Digilent is responsible for creating demos for them as well. This is because platform specific timing constraints are need to use most current and future ZMODs. For people like me who opt to forgo the Digilent AXI IP designed for the ZMODs we are responsible for out own designs and related constraint files.

Edited by zygot

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1 minute ago, zygot said:

I should add that, as they sprinkle ZMOD goodness about on new platforms. Digilent is responsible for creating demos for them as well. This is because platform specific timing constraints are need to use most current and future ZMODs. For people like me who opt to forgo the Digilent AXI IP designed for the ZMODs we are responsible for out own designs and related constraint files.

Yes they are.  I was able to upgrade the low level controller so that isn't the problem but the AXI controller seems to not have abstraction definitions for the ports on it.  I suspect I need to download an upgrade to the thing since what I found was listed as "pre-production."

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