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Pier

Zybo z7 evaluation

Question

How could be  possible to implement the design shown in attached video?

in the video the arrays are 600 samples each, but i would go for bigger arrays as possible and 24 or 32 bit values

i'm planning to use a zybo z7 board

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Hi Pier,

I'm a bit confused, where do the signals come from? Do you have two external sources or do you generate them in the FPGA? Similarly, do you want to a analog output of the resulting signal or do you only need the samples? 

-Ciprian

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Hi Ciprian

The video is just an example,

 

The arrays on the left are stored on block memory as rom memory, The resulting array have to be stored in ddr memory.

The control (that  i do using with mouse) of the operation will be an external signal coming from adc

The resulting array will be used as wavetable for a lookup audio oscillator.

At this stage of the design i only need samples. The design is made of many similar operations, until you read the resulting waveform

 I cannot calculate on the fly for the operations that are involved

 

I would like to handle this kind of arrays [31:0] [16383:0] and try to code what you see in the video in a block to evaluate how many of this processes i could instance

Thx for your patience,

Pier

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This is more of a FPGA size question then a board specific question. We have other boards with the same FPGA, Arty Z7 for example.

As for your problem, you might be able to generate the required array, depending on the -20 or -10 variant of the Zybo Z7 and depending on the way you write the HDL code. The best I can recommend is build your project in Vivado for the Zybo Z7 and look at the resource consumption and limitations.

-Ciprian

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