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D@n

Arty A7 flash clock

Question

Xilinx requires the flash clock be connected to a special pin.  The official way of accessing this pin is through the STARTUPE primitive.  This limits the clock speed to 1/2 of the system clock speed, since there are no ODDR primitives available when going through the STARTUPE primitive.  (Yes, you could do a CDC, but this gets annoying ...)

The Arty (used to?) have an alternate method of accessing this pin via a secondary I/O pin also connected to this same line.  According to the reference manual, this wire connects to pin L16.

I just downloaded the A7100T master XDC file, however, and I don't see this secondary pin defined in the XDC file anywhere.

Did it get removed?  And if so, does your reference information also need to change?  If not, shouldn't it be put back into the XDC file?

As a customer, I will be disappointed if it was removed, since it will now mean that access to the flash is 2x slower than before.

Dan

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6 hours ago, [email protected] said:

Xilinx requires the flash clock be connected to a special pin

Hey, you've stumped me there. What's a flash clock? I'm assuming that this is a configuration issue.

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@zygot,

I'm referring to the SPI SCK pin headed to the configuration flash.  It's used during configuration, but can also be used by a user design later using either the STARTUPE primitive, or (on the Arty--at least the way it was) using a second pin that was also tied to the same SCK wire leading to the flash.  (There reference page shows a resistor between the two ...)

Dan

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@[email protected],

Oh, you mean the CCLK_0 pin;. I could be wrong but as I remember it, the configuration clock if free for use in your HDL design after configuration. I'm thinking that you can just use pin L!6 for whatever purposes that you want. Perhaps I'm looking at an old schematic. You should be able to use CCLK after configuration though the only thing QSPI_SCK is tied to are the FLASH devices. I suppose that you are trying to speed up FLASH data transfers?

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@zygot,

Now I think you understand exactly what I mean.  The flash memory is quite useful for ... whatever purpose.  It's especially useful when playing with CPU's, and wanting your design to start from a known program.  Flash is known for being slow.  The particular flash chips that've been used on the Arty are rated for a clock of 108MHz.  If you have a system clock of anything lower than 108 MHz, though, you'll either need to use an ODDR primitive to set the pin--something not available to you when going through the STARTUPE2 primitive--or suffer a 2x speed loss when going through flash.  Since I like running at a 100MHz system clock (or near that amount) *and* a 100MHz QSPI_SCK, getting the full performance out of the flash requires a general purpose I/O pin.

Looking over the schematic and the reference manual, this I/O pin is connected to L16.

It's not listed in the XDC file.

Hence my question.

My best guess is either 1) they forgot to include it in the XDC file, or 2) thought (for some reason) it would be better left out of the master XDC file.  I had been afraid this capability was taken off the board, but seeing it on the schematic gives me some assurance that it's still around.

Dan

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Well, until someone from Digilent has a better explanation, I'll just point out that this wouldn't be the first time I've seen their constraints files niss pin assignments. I've never known their schematics to be wrong yet. I make a habit of checking the schematics anyway before using pins and interfaces that I've not previously used.

Just check the configuration user's manual to confirm my recollection about CCLK post configuration; but I'm betting that you are good to go.

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Hi @[email protected] and @zygot,

I apologize for the long delay.

The pin is indeed still present on L16 on page 6 of the schematic and is almost certainly the intended use of that pin. I'm not sure why it's not the .xdc (or if it ever was, since realistically the .xdc was copied over from the original Arty .xdc before a bunch of other Arty branded boards were introduced), so I'm working to confirm that there isn't some reason that the pin should not be in the .xdc and then we get it added in.

Thanks,
JColvin

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