Xilinx requires the flash clock be connected to a special pin. The official way of accessing this pin is through the STARTUPE primitive. This limits the clock speed to 1/2 of the system clock speed, since there are no ODDR primitives available when going through the STARTUPE primitive. (Yes, you could do a CDC, but this gets annoying ...)
The Arty (used to?) have an alternate method of accessing this pin via a secondary I/O pin also connected to this same line. According to the reference manual, this wire connects to pin L16.
I just downloaded the A7100T master XDC file, however, and I don't see this secondary pin defined in the XDC file anywhere.
Did it get removed? And if so, does your reference information also need to change? If not, shouldn't it be put back into the XDC file?
As a customer, I will be disappointed if it was removed, since it will now mean that access to the flash is 2x slower than before.
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D@n
Xilinx requires the flash clock be connected to a special pin. The official way of accessing this pin is through the STARTUPE primitive. This limits the clock speed to 1/2 of the system clock speed, since there are no ODDR primitives available when going through the STARTUPE primitive. (Yes, you could do a CDC, but this gets annoying ...)
The Arty (used to?) have an alternate method of accessing this pin via a secondary I/O pin also connected to this same line. According to the reference manual, this wire connects to pin L16.
I just downloaded the A7100T master XDC file, however, and I don't see this secondary pin defined in the XDC file anywhere.
Did it get removed? And if so, does your reference information also need to change? If not, shouldn't it be put back into the XDC file?
As a customer, I will be disappointed if it was removed, since it will now mean that access to the flash is 2x slower than before.
Dan
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