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MikeA

No device found with Vivado and HS3

Question

I'm using Vivado 2019.2 with the JTAG-HS3 on a custom carrier mated with the picozed 7015 board.

Vivado does not detect the FPGA, but adept does. There are no other JTAG devices in the chain.

I've tried lowering the frequency in vivado, but I'm not having any luck with detection.

In case this matters: the vivado project is originally setup for the picozed FMC v2 carrier board, which my board design is based on. I've used the HS3 on the FMC v2 board without any issues.

vivado.png.e109eaefb45d55bf023252ac4617520f.png

 

adept.png.9809b1d1dd9f3c9360cbf78e01a59bfa.png

Any suggestions on what to try next?

Thanks in advanced!

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I was able to find the issue. PG_MODULE was being driven too low and I fixed the offending portion.

This might be helpful for others experiencing something similar. What I actually saw on JTAG was it resetting and going into Shift-DR. Then, the FPGA's IDCODE was shifted out, then zeroes. When tracing this on the FMC v2 carrier, I noticed the ARM IDCODE coming after. The PL was clearly being powered on my carrier and the PS supplies are all on the picozed, except for 5V and PG_MODULE. Then I noticed PG_MODULE (connected to PS_POR_B) was not high enough and fixed it.

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@MikeA

I just connected a JTAG-HS3 to J15 of the Zed board and Vivado 2019.2 was able to detect both the ARM and PL on my Windows 10 PC.

jtag-hs3_works_with_vivado_2019.2-01.JPG.1249deb8de982e246464a19ff49273fa.JPG

 

 

It's rather odd that Adept can see the 7015 on your board but Vivado cannot. I looked at the PicoZed schematic and the JTAG lines are referenced at 3.3V with 4.7K pull-ups to 3.3V. Do you have any additional pull-up or pull-down resistors on your board? What about series resistors or buffers between the 14-pin header and the JTAG lines? One other thing: are you supplying power (probably should be 3.3V) to pin 2 of your 14-pin JTAG header?

Thanks,
Michael

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