SPI Accelerometer Tester: VHDL, Verilog, or IPI-BD

[Tim S. 8]

https://github.com/timothystotts/fpga-serial-acl-tester-1

fpga-serial-acl-tester-1

A small FPGA project of different implementations for testing Measurement and Activity Events of a SPI accelerometer

Refer to: ./Serial ACL Readings Tester.pdf

and: ./ACL-Tester-Design-Documents/ACL-Tester-Design-Diagrams.pdf

[Tim S. 8]

Hi,

For those who may wish to examine this project for potential reuse, I created an architecture diagram of the design.

Best,

Tim S.

[Tim S. 8]

Some updates were made to the fpga-serial-acl-tester-1 project. The HDL architecture was updated to better software practices.

ACL-Tester-Design-Diagrams-Architecture 1.pdf

[Tim S. 8]

Some updates were made to the fpga-serial-acl-tester-1 project. The HDL architecture was updated to better software practices.

[Tim S. 8]

Some further updates were made to the VHDL sources to include usage of a Pmod SSD at Pmod Jack A. These updates are committed at branch feature/ssd_with_presets.

Additionally, the FSM diagrams of the aforementioned architecture sketch are now comprehensive in the Documents folder.

[Tim S. 8]

This project was upgraded to Vivado/Vitis 2020.2 .

[Tim S. 8]

I'd like to mention that within this project I designed in both VHDL-2008 and Verilog-2001 a Pmod SPI Mode 0 driver that enables design of a companion peripheral driver specific to the Peripheral device on the SPI bus.

These two new diagrams may explain how pmod_generic_spi_solo.v or pmod_generic_spi_solo.vhdl, as well as the Peripheral driver coding style, can be reused for each SPI Pmod in the design.

Regards,

Tim S.