SPI Accelerometer Tester: VHDL, Verilog, or IPI-BD


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  • 2 weeks later...
  • 2 weeks later...

Some further updates were made to the VHDL sources to include usage of a Pmod SSD at Pmod Jack A. These updates are committed at branch feature/ssd_with_presets.

Additionally, the FSM diagrams of the aforementioned architecture sketch are now comprehensive in the Documents folder.

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  • 4 months later...
  • 2 months later...

I'd like to mention that within this project I designed in both VHDL-2008 and Verilog-2001 a Pmod SPI Mode 0 driver that enables design of a companion peripheral driver specific to the Peripheral device on the SPI bus.

These two new diagrams may explain how pmod_generic_spi_solo.v or pmod_generic_spi_solo.vhdl, as well as the Peripheral driver coding style, can be reused for each SPI Pmod in the design.

Regards,

Tim S.

 

 

ACL-Tester-Design-Diagrams-CLS-ports-internal.thumb.png.73efbc4cead7613da20c4c292b51fc38.png 

 

 

 

ACL-Tester-Design-Diagrams-ACL2-ports-internal.thumb.png.cb9f618782c09ade872081fd92bd0066.png

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