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Basys3 Simulation


I am using Windows XP and Vivado 2014.2 webPack. I follow this tutorial: https://github.com/charlespittman/massive-ironman/blob/master/school/elec_311/Xilinx%20ISE%20WebPACK%20VHDL%20Tutorial.pdf It is little bit old. But I succeed to fix what needed (for example to create suitable xdc instead of ucf), and compile successfully (it generate bitstream file). My question is as follow. I have basys3 board, but as first step I want to make some simulations only on computer. For example I want (virtually) to press user switches, and look at (virtual) led. With what software I can do this?

Edited by Josh
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Hi Pismo,


You can do (almost) this using the built-in simulator to tool in Vivado.


So say you have created a simple design like this, that just connects the switches to the LEDs:

library IEEE;
entity design is
    Port ( switches : in  STD_LOGIC_VECTOR (7 downto 0);
           leds : out  STD_LOGIC_VECTOR (7 downto 0));
end design;
architecture Behavioral of design is
   -- Do nothing but set the outputs to the inputs.
   leds <= switches;
end Behavioral;

You then need to add a new VHDL test bench. There is nothing that special about test benches, except the top level design has no inputs or outputs, and you are allowed to use statements or structures that can not be implemented in an FPGA (such as 'wait for 100 ns;'). The test bench then twiddles the inputs to the unit under test, and you can then see how it reacts to the inputs. This is at the same time very simple and powerful, but at the same time overly complex and too simplistic. I just find it weird...


You need to add a test bench with the "Add Sources" Flow Navigator option, and select "Add or Create Simulation Source". You don't need to give it any inputs or outputs, but by default Vivado is unhelpful and adds an empty "Port ();" statement in the entity declaration that gives the file a syntax error. This is one time where ISE is far superior, as it auto-creates the body of the test bench - so much so I would recommend you play with it first in ISE if you have the option.

Anyhow, here is what the test bench could look like:
USE ieee.std_logic_1164.ALL;
ENTITY test_bench IS
END test_bench;
ARCHITECTURE behavior OF test_bench IS 
    COMPONENT design
    PORT( switches : IN  std_logic_vector(7 downto 0);
          leds : OUT  std_logic_vector(7 downto 0));
   signal switches : std_logic_vector(7 downto 0) := (others => '0');
   signal leds : std_logic_vector(7 downto 0);
   uut: design PORT MAP (
          switches => switches,
          leds => leds
   -- Stimulus process
   stim_proc: process
      switches <= "00000000";
      wait for 100 ns; 
      switches <= "00000001";
      wait for 100 ns; 
      switches <= "00000011";
      wait for 100 ns; 
      switches <= "00000111";
      wait for 100 ns; 
      switches <= "00001111";
      wait for 100 ns; 
      switches <= "11111111";
   end process;
In Vivado you then need to use the "Simulator Settings" Flow Navigator option to select the top level for your simulation (in this case the test_bench module), and then "Run Simulation" Flow Navigator option to start the simulation. You will then a chart detailing the first microsecond in the life of your design.
Simulating up to a small fraction of a second is possible with simple designs or very slow clock rates, but anything longer than about 1ms with a 50MHz clock will start getting painfully slow, as the simulator will need to evaluate and record all the state changes for the logic in the design. Even verifying a simple VGA test signal generator for a single frame can be annoyingly slow!

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