Title says it all. I've tried various baud rates. I've tried using the wizard to generate a clock that I then divide to see if it's more accurate. Right now, the latest attempt divides my 100MHz clock by 1k to get a clean 100k baud. I'm using the analog discovery 2 to spy on BB1 (first breadboard pin) on my Anvyl. My code waits for a button press to repeatedly send out a simple hard-coded message, which then resets on the button release. The LEDs are just for primitive version control (so I know what program is on the board). Here's the source for both the repeater and the clock divider:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity msg_repeater is
Port ( clk : in STD_LOGIC;
btn : in STD_LOGIC;
tx : out STD_LOGIC;
led : out STD_LOGIC_VECTOR (3 DOWNTO 0));
end msg_repeater;
architecture Behavioral of msg_repeater is
component clk_div is
Port ( CLK_IN : in STD_LOGIC;
CLK_OUT : out STD_LOGIC);
end component;
-- Binary message content:
-- "01010100" T
-- "01000101" E
-- "01010011" S
-- "01010100" T
-- "00100000" space (0 and 1 added on sides of each character for UART protocol)
signal msg : std_logic_vector (49 downto 0) := "00101010010010001011001010011100101010010001000001";
signal msg_index : natural range 0 to 50 := 0;
signal int_tick : std_logic := '0';
signal baud_tick : std_logic := '0';
begin
clk_div_inst : clk_div
port map(
CLK_IN => clk,
CLK_OUT => baud_tick
);
process(baud_tick)
begin
if rising_edge(baud_tick) then
if(btn = '1') then
if(msg_index = 50) then
msg_index <= 0;
end if;
tx <= msg(msg_index);
msg_index <= msg_index + 1;
else
tx <= '1';
msg_index <= 0;
end if;
end if;
end process;
led <= "1010";
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity clk_div is
Port ( CLK_IN : in STD_LOGIC;
CLK_OUT : out STD_LOGIC);
end clk_div;
architecture Behavioral of clk_div is
--signal clkCount : std_logic_vector (3 downto 0) := "0000"; --counter for input clock
signal clkCount : std_logic_vector (9 downto 0) := "0000000000"; --counter for input clock
signal outTick : std_logic := '0';
--constant clk_check : std_logic_vector := "1010";
constant clk_check : std_logic_vector := "1111101000";
begin
process(CLK_IN)
begin
if CLK_IN'Event and CLK_IN = '1' then
if(clkCount = clk_check) then
outTick <= '1';
clkCount <= "0000000000";
else
outTick <= '0';
clkCount <= clkCount + 1;
end if;
end if;
end process;
CLK_OUT <= outTick;
end Behavioral;
Question
CPerez10
Title says it all. I've tried various baud rates. I've tried using the wizard to generate a clock that I then divide to see if it's more accurate. Right now, the latest attempt divides my 100MHz clock by 1k to get a clean 100k baud. I'm using the analog discovery 2 to spy on BB1 (first breadboard pin) on my Anvyl. My code waits for a button press to repeatedly send out a simple hard-coded message, which then resets on the button release. The LEDs are just for primitive version control (so I know what program is on the board). Here's the source for both the repeater and the clock divider:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity clk_div is Port ( CLK_IN : in STD_LOGIC; CLK_OUT : out STD_LOGIC); end clk_div; architecture Behavioral of clk_div is --signal clkCount : std_logic_vector (3 downto 0) := "0000"; --counter for input clock signal clkCount : std_logic_vector (9 downto 0) := "0000000000"; --counter for input clock signal outTick : std_logic := '0'; --constant clk_check : std_logic_vector := "1010"; constant clk_check : std_logic_vector := "1111101000"; begin process(CLK_IN) begin if CLK_IN'Event and CLK_IN = '1' then if(clkCount = clk_check) then outTick <= '1'; clkCount <= "0000000000"; else outTick <= '0'; clkCount <= clkCount + 1; end if; end if; end process; CLK_OUT <= outTick; end Behavioral;
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