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Updated vivado-library drivers


Tim S.

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Hi. As an activity of self-instruction in FSM design, I have created nine projects for the Arty-A7-100T and one project for the Zybo-Z7-20. Each project is a basic learning in AXI block diagram design, FreeRTOS and standalone code execution, or fully custom drivers in VHDL and Verilog.

One of the projects I created used Vivado 2020.1 and Vitis 2020.1 to create a Pmod SF3 byte-by-byte memory tester. Out of necessity, I updated the drivers for Pmod SF3, Pmod CLS, and PWM 2.0. Before these updates, Pmod SF3 would not operate properly with FreeRTOS. The driver I wrote is called PmodSF3_freertos and now provides functionality when using FreeRTOS instead of standalone; and functions correctly so long as the QSPI component of the Pmod SF3 Vivado IP is updated to use of a FIFO of 256 beats instead of 16 beats.

The software drivers of the Pmod SF3 and Pmod CLS require an update to the latest xspi driver so that their compilation does not overwrite the regular xspi driver during Platform compilation. In addition, their Makefile requires an update to successfully complete compilation and adding of object files to archive libxil.a . Also, Vitis 2020.1 executes GCC with -Wall and -Wextra options, which make the compiler fail on the majority of warnings (those that are coding style blemishes and possibly errors). One example is the compiler will fail to compile a file if a warning is generated that a function contains an unused variable.

What is the most appropriate and beneficial way for me to give these driver changes (as an example) back to Digilent or the community?

Tim S.

 

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