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pmod hygro not reading


mukunda

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hi i used the example files and designed my own block diagram due to comparability issues and was able to display results on tera term but the readings are off and keep decreasing by 10 until it loops and restarts and this reading gets shown even without the sensor being plugged in

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Months ago, I wrote a Pmod HYGRO driver in VHDL without block diagram. The Pmod HYGRO's I2C requirements are odd. I'd be glad to mention my findings if you are debugging waveform or message-order issues for reading the HYGRO's measurement registers.

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On 7/4/2020 at 11:08 AM, Tim S. said:

Months ago, I wrote a Pmod HYGRO driver in VHDL without block diagram. The Pmod HYGRO's I2C requirements are odd. I'd be glad to mention my findings if you are debugging waveform or message-order issues for reading the HYGRO's measurement registers.

Do you mind sharing the Pmod HYGRO VHDL driver file? I am trying to read the data via UART protocol, it seems that I cannot identify if the sensor is working or not. I am not using Vivado IP now, the project is based on vhdl files. There is another vhdl source provided by Scott. It does not help me so far.

https://forum.digikey.com/t/humidity-and-temperature-sensor-pmod-controller-vhdl/13064

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Well, I worked out just now. I just set the sys_clk to 100MHz, and connect the pmod interface ja(3 to 4) to scl, sda. I am using ArtyA7-100T, I am not sure why picking up 100 MHz as the internal clock frequency of board is 450MHz. I get the 14 bit data from hum and tem registers. The VHDL source file is from digikey as is the last post.

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On 4/4/2022 at 12:40 PM, Model92 said:

Do you mind sharing the Pmod HYGRO VHDL driver file? I am trying to read the data via UART protocol, it seems that I cannot identify if the sensor is working or not. I am not using Vivado IP now, the project is based on vhdl files. There is another vhdl source provided by Scott. It does not help me so far.

https://forum.digikey.com/t/humidity-and-temperature-sensor-pmod-controller-vhdl/13064

@Model92, you can find a small project I wrote for the Pmod HYGRO at:

https://github.com/timothystotts/fpga-iic-hygro-tester-1

I do apologize. The driver is in Verilog-2001, not in VHDL. I have authored some of my examples in one, two, or three languages. I haven't authored all of the examples in all three languages (Verilog, SystemVerilog, VHDL). It should still be useful.

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