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MIPI CSI-2 Receiver IP


blake@praesum.com

Question

I have one of the FMC Pcam adapters and had some questions about the diligent provided MIPI IP, I pulled down the Zybo Z7 Pcam reference design to get an idea on what IP is used and am a bit confused.

In the project there is a MIPI_D_PHY block and a MIPI_CSI_2_RX block, both marked as Pre-Production. In the project they are both identified as Digilent IP. The Xilinx IP Catalog has versions of both these, the CSI-2 specifically has a paid license. Are the Digilent blocks completely independent of the Xilinx IP? I'm in the process of designing a sensor demo for multiple boards and was hoping this MIPI CSI-2 block would be portable.

Ideally I'd be like to use the MIPI CSI-2 Rx block to target different boards (ZCU102/104) and even other FPGA families (Microsemi's Polarfire). Is this possible with the included IP in the Zybo reference project?

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Hi Blake,

Our MIPI offering published at https://github.com/Digilent/vivado-library/tree/master/ip is a limited functionality implementation for those without access to the specs or licensed IP. We are commited to providing open-source implementations that people can learn from. The Digilent D-PHY Receiver works with the D-PHY I/O separated into LVDS high-speed and LVCMOS low-power buses, as implemented on the Zybo Z7.

However, if you are looking for full-featured MIPI IPs, have a look at Xilinx's offering: D-PHY has been free for some time and CSI-2 just became free in Vivado 2020.1. Xilinx's D-PHY supports direct D-PHY I/O interfacing (UltraScale+) and LVDS/LVCMOS-separated (pre-UltraScale+).

There are important restrictions on the system. Take a look here:

https://reference.digilentinc.com/reference/add-ons/fmc-pcam-adapter/reference-manual#fpga_io_architecture_compatibility

 

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