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Simple question regarding Anvyl Spartan 6 clock frequency

Question

I read on the Anvyl reference manual that the spartan 6 chip is capable of 500MHz clock speeds, but all the demos seem to be based off of 100MHz. Is this because it's using the on-board crystal oscillator, or is it because of the speed setting in the project properties?

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Posted (edited)

Hi,

as a simple (oversimplified?) answer, designing for higher clock speed requires higher effort (possibly "much" higher effort), and the resulting optimizations make the code harder to work with.

Using the clocking wizard to generate a 500 MHz PLL is easy (try it). But writing logic at those frequencies is a different story (e.g. try to implement a conventional counter that divides down to 1 Hz. Why do all those XYX_CARRY signals show up in the timing report already at synthesis?). You also need to distinguish between what is feasible in plain logic fabric, and what can be done with dedicated "hard-macro" IP blocks such as SERDES.

Edited by xc6lx45

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