Differential outputs on Arty-A7

[jamesW]

Hi, I am experimenting with differential outputs on the Arty A7. For this, I am using the 100MHz clock and have instantiated an OBUFDS --

 SYS_CLK_OBUFDS : OBUFDS
    generic map(
        IOSTANDARD => "TMDS_33"
    )
    port map(
        I => CLK100MHZ,
        O => sys_clk_out_p,
        OB => sys_clk_out_n
    ); 

The .xdc file has the following --

## Pmod Header JB
set_property -dict { PACKAGE_PIN E15   IOSTANDARD TMDS_33 } [get_ports { sys_clk_out_p }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1]
set_property -dict { PACKAGE_PIN E16   IOSTANDARD TMDS_33 } [get_ports { sys_clk_out_n }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1]

Synthesis & implementation are fine and I can generate a bitstream, but I see no output on these pins (just 0v).

FYI, if I use a single-ended output (via OBUF) as shown below, it works fine --

SYS_CLK_OBUF : OBUF
    generic map(
        IOSTANDARD => "LVCMOS33"
    )
    port map(
        I => CLK100MHZ,
        O => sys_clk_out
    ); 

With the .xdc file constraint --

## Pmod Header JD
set_property -dict { PACKAGE_PIN D4    IOSTANDARD LVCMOS33 } [get_ports { sys_clk_out }]; #IO_L11N_T1_SRCC_35 Sch=jd[1]

Any idea what I am missing? 

Thanks.

[zygot]

1 hour ago, jamesW said:

Any idea what I am missing? 

You can figure this out for yourself by going back to the first step of your project. This was reading the Series 7 Select IO User's Manual. Pay attention to the sections on TMDS33 IOSTANDARD, particularly study the termination diagrams. Then look at the schematic for your board and see if you can follow them.

Are you driving your sys_clk_p and sys_clk_n on clock capable pins? While you are getting the Select IO User's Manual take some time to brows through the Series 7 Clocking User's Manual.

Edited June 8, 2020 by zygot

[jamesW]

9 hours ago, zygot said:

You can figure this out for yourself by going back to the first step of your project. This was reading the Series 7 Select IO User's Manual. Pay attention to the sections on TMDS33 IOSTANDARD, particularly study the termination diagrams. 

Are you referring to UG471? If so, I looked through the sections pertaining to TMDS_33. Just going back through it, the most pertinent section appears to be on P95:
   TMDS inputs require a 50ohm pull-up and no diff term resistor
   Bank voltage is 3V3 and TMDS is available on HR banks 
   TMDS_33 IOSTANDARD supports OBUFDS 

The first point, above, isn't relevant as I'm configuring outputs. The second and third points are satisfied by the design.

There are termination diagrams in the appendices, are you referring to these? 
 

10 hours ago, zygot said:

Are you driving your sys_clk_p and sys_clk_n on clock capable pins? 

Something which also crossed my mind when I first looked at this, but I don't think this is relevant for outputs? e.g. If you look at the clocking resources guide, it explicitly mentions clock inputs should be routed via clock capable pins. It's a bit vague, as it mentions 'clock capable I/O' in some places, but I think that clocks exported from the FPGA should be brought out via an ODDR + (OBUF or OBUFDS) and do not need to be connected to clock capable pins.
 

[asmi]

13 hours ago, zygot said:

Are you driving your sys_clk_p and sys_clk_n on clock capable pins? While you are getting the Select IO User's Manual take some time to brows through the Series 7 Clocking User's Manual.

CC pins are only relevant for inputs AFAIK. Besides E15/E16 are actually CC pins.

3 hours ago, jamesW said:

The first point, above, isn't relevant as I'm configuring outputs.

TMDS uses current driver, so it can't work without termination.

[zygot]

1 hour ago, asmi said:

CC pins are only relevant for inputs AFAIK. Besides E15/E16 are actually CC pins

I stand corrected, and didn't take the time to look at the schematic. Thanks. On the plus side, now that I've been shamed into being a bit more responsible, and seeing the Arty A7 schematic, it does look like your choice of IO pins means that the standard habit of Digilent IO using 200 ohm series resistors isn't a concern.

I guess that I wasn't thinking that the fact that termination as a requirement for differential drivers isn't obvious. Think of them as similar to Open Collector (Drain) or ECL PECL. In my defense UG471 does say "requires external 50 ohm pull-up resistors". It mentions termination on the inputs but as @asmi has pointed out differential drivers don't do much unless connected to proper termination ( input or not ) as the termination completes the driver circuit. BTW, when the receiving end is powered by a different Vcc than the driver you can get into trouble if Vcc for both the driver and receiver aren't powered on simultaneously. This seems to be somewhat of a shortcoming for a video standard where monitors are usually different equipment than video source equipment, each with their own power supplies. Still, you can and should design your circuit for such eventualities. Driving current into your FPGA IO bank Vccio rails through IO pins isn't desirable at all.

Silly me, I thought that UG471 had a termination diagram for TMDS33... I seem to have gotten that wrong. Apologies.

 

Edited June 9, 2020 by zygot

[zygot]

Final thought. Though reading FPGA vendor literature is a good idea before trying to design a project, if you are going to connect your FPGA IO pins to things it's a also a good idea to educate yourself on specific logic standards. You can pretend that FPGA development is just another kind of software development, at least in the beginning of your own development, as long as everything stays inside the device. Once you start connecting pins to other devices you are doing digital logic design and there's no pretending anymore.

[jamesW]

On 6/9/2020 at 2:32 AM, asmi said:

TMDS uses current driver, so it can't work without termination.

Connected resistors, as per your comment. Outputs now look fine.

Thank you

[qamesh]

@jamesWHello ,  I am currently facing the same issue and Would like to ask the size of the termination resistor in your case?.. as I see in the Manual E15/E16 have zero internal resistor in series, did you connect any other resistor in series externally?

regards