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Arty Z7 peripheral connections


Posted (edited)

I am trying to use buttons (BTN0 and BTN1) in my programmable logic to control several general purpose I/O pins (IO0-IO13). I am using the I/O pins to power a circuit on a breadboard that should visually change according to a state machine that I have simulated and found works as expected. But when I try to implement the design, I get this error:


[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn0_IBUF] >

    btn0_IBUF_inst (IBUF.O) is locked to IOB_X1Y142
     and btn0_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

When I include the line that demotes this error to a warning in the constraints file, "set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets btn0_IBUF]" my circuit shows no signs of the state machine changing states. i.e. the buttons don't affect the circuit as they should.

I have tried connecting the buttons to an LED on the board as well to see if they were broken, but they worked on an LED, just not when trying to change the values of the I/O pins.

I have tried looking online for detailed diagrams of how the peripherals (the buttons and I/O pins) are connected to the FPGA but could not find anything especially useful. If anyone could explain to me how they are connected or could be connected I would be very grateful.



Edit: fixed

Yes, you are correct. The problem was that I was using "always_ff( posedge btn0, posedge btn1)" to trigger changes in my state machine. I didn't realize you had to use a clock to trigger things in an always_ff block. I would be, and I'm sure other beginners in digital electronics would also, be interested in why this is not allowed.


Edited by bobsmith
fixed original problem

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Posted (edited)


The Arty Z7's Reference Manual (Basic I/O and Shield Connector sections) and Schematic (sheets 1, 2, and 9) have information on how these components are connected.

All four buttons are connected to pins on FPGA Bank 35 with resistors to pull down the pin while the button is open, and protect the FPGA pin from the voltage rail while the button is closed. IO pins 0-13 are connected to FPGA Bank 34 via current limiting resistors.

The buttons can be noisy, so it may be worthwhile to debounce their signals, if you are not doing so already. Checking the debouncer output on an LED, or creating a simple toggle circuit to control an LED from a button could also be useful in figuring out if the buttons states are being captured as you expect.

Edit: a coworker pointed out this Xilinx forum thread: https://forums.xilinx.com/t5/Implementation/Poor-placement-for-routing-between-an-IO-pin-and-BUFG/td-p/784930

There is some additional information in there about what the warning related to BUFG is about. Some pin may be being misinterpreted as a clock or a reset by the tools, which is causing the poor placement. I'd recommend checking your design's edge sensitivities - in Verilog, [email protected](..., posedge btn) would be bad, for example.


Hope this helps,



Edited by artvvb
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