Timing issues when Integrating multiple .VHD files

[Luke Abela]

Good day,

 

I have an issue regarding integration of .VHD files in a format of hierarchal VHDL. I have written an LVDS DDR reception protocol in VHDL, and have done a behavioural simulation and a post-implementation timing simulation of this file. Both simulations returned the intended results. I then went to call this LVDS file from a TOP file. I assigned physical inputs (NEXYS4DDR) to connect to my LVDS protocol, and assigned the output to test LEDs and ILA (my intention is to set and see a repeated digital word receieved and output), however, when I ran the post-implementation timing simulation with the top file, my results were altered (my behavioural simulation of top file was successful). Has anyone ever encountered a similar issue? Any and all help welcome.

 

Regards,
Luke

[D@n]

@Luke Abela,

Help me out here, what are you trying to do?  Build a DDR3 SDRAM controller?  Also, what's the system clock rate you are building to?

Thanks!

Dan

[zygot]

2 hours ago, Luke Abela said:

I have written an LVDS DDR reception protocol in VHDL, and have done a behavioural simulation

Ok, as I understand it you have a VDL entity that you did a behavioral simulation on. I assume that you mean that you created a testbench in VHDL that drove the inputs to your entity and you looked at the output results. So far so good, perhaps.

 

2 hours ago, Luke Abela said:

I then went to call this LVDS file from a TOP file.

So then you instantiated the previous LVDS entity as a component into a toplevel file and connected the outputs to physical pins, though this is irrelevant as you are still doing simulation.

I then went to call this LVDS file from a TOP file.

2 hours ago, Luke Abela said:

when I ran the post-implementation timing simulation with the top file, my results were altered

Ok, this really isn't helping me understand what your question is. First of all you need a testbench to drive the entity that you are simulating whether its pre-synthesis or post place and route. For simulation the testbench is the toplevel design file. If you are doing all of that then you need to be more descriptive of your issue.