No BVALID response from MIG AXI4 controller after few successsful transactions

[Raghav]

Hi,

I am using Kintex-7 on genesys2 and loading image data on to DDR.

I see proper writes from address = 0x0 to 0x800 while loading the image to DDR. MIG data width is 32 bytes, so I make awlen=1 to send TWO 32bytes back to back to write one cache line.

But for next address = 0x840, I do NOT see "bvalid" though "bready" is high from my AXI master. MIG has accepted awvalid and wvalid (as I can see awready and wready high from MIG).
Can it be issue with MIG_AXI4 or DDR ?

 

 

One this is I am NOT asserting "WLAST" from master for last beat of the burst transaction? Does MIG requires it? because previous many transactions went successful without WLAST.

Can you please suggest any other signals to monitor on ILA which can help debug.
I am not sure what can be the problem now !

Thanks,
Raghav

[D@n]

@Raghav,

AXI requires WLAST.  Whether or not the MIG controller does is irrelevant.  If you are using the AXI interface, then AXI requires it.

Dan

[Raghav]

@D@n,

That was RTL bug in AXI master driver which I tried to re-use. I have fixed it now.   I agree wlast can be additional useful info for slave to let it know about last beat of burst.

But slave can also figure out by burst type, awlen, and awsize. But here, MIG gave successful Bvalid with good Bresp even without WLAST for many transactions., so I thought it is figuring it out about last beat of burst. I am synthesizing again with fix on WLAST.

[Raghav]

Just updating for benefit of others. MIG actually expects WLAST assertion. With this fix, Tests are working fine on FPGA. Even without WLAST, bvalid responses are observed on ILA but some transaction at some point was getting hung because of NO response.