Address Alignment MIG AXI7 versus MIG NATIVE on KIntex-7 DDR3

[Raghav]

Hi,

Lets say below are my 2 cache lines. Since Kintex-7 has DDR3 which is 256 bit wide. Can you please clarify below?

 

From working system , from ILA on MIG native bus,  Below is the pattern.

Cache line is size = 64BYTES (512 bits) for the system I am using. It seems 4Bytes per word and 8 WORDS PER transaction, so 32bytes (256bit). But why we are NOT aligning address to byte ?! Why 0x8 for second 256bit , why not 0x20.?

Cache line 1 First Half: Address = 0x0 , 256 bit

Cache line 1 Second Half: Address = 0x8 , 256 bit

Cache line 2 First half : 0x10 , 256 bit

Cache line 2 Second half : 0x18 , 256 bit

Now I need AXI4 interface based MIG. What should be the address pattern?  Is it simple byte addressable like 0x0, 0x40 for consecutive cache lines . I am using master agent with arlen of 2 beats to get 64bytes. Can't I give 0x40 for second line with arlen of 2 beats to get back to back two 256 bits?

Thank you!

Raghav

[D@n]

@Raghav,

I'm not sure I follow your whole question, but I do know this: if you set ARLEN to 2 you will get *three* RVALID responses, not two.  If you want a 256 bit return, you'd also need to make certain you set AxSIZE appropriately as well.

There are also a lot of reasons why transactions might not be aligned with bus words.  For example, if the MicroBlaze core were configured for a 64-bit bus, it might go though a bus expander to get to a 512-bit bus.  That might mean that the maximum request size would only ever be 64-bits, even though carried in a 512-bit bus.  Since I don't know the details of how MicroBlaze is constructed, I'm not sure of the answer on this.

Dan