A Test bench for a counter with clock instantiated

[MsDh]

Hi everyone.
I had difficulties about clock IP instantiation and posted my question here. Someone responded very soon and helped me to successfully instantiate the IP clock for my first time. Now I think I need to start a new thread with rest of the questions about this small project.
My main module and IP clock is attached along with my Constraint file.

Please answer my questions and let me learn from you. Again I am new  to Vivado and Digilent Zedboard but I love to learn.

1. I would like to know what other line of codes are useless (other than commented lines) in my constraint file? 
2. I would like to know if there is a better way to instantiate a clock at desired rate of 10 Hz or any slow clock?
3. If I want to design a test bench how do I connect the system clock to my design in order to simulate it?
   Do I need to define an initial block of clock inside my test bench? How does it work?

This is a link to previous posting that was initially asking how to instantiate a clock IP: 

 

clk_constraint.xdc clk_wiz_0.v dcm_example.v

[D@n]

@MsDh,

I think we need to be careful with terms.  There are two separate things that can be called a "clock".

• One is a logic signal, generated by your core, that toggles at the rate you have listed.  To create such a clock at 10Hz you don't normally need to use any of the clocking wizards you just need a counter.  I'm going to call this a "logic clock".
• This is very different from a fabric clock which you can transition your signals on.  If you want to trigger logic using the rising_edge construct in VHDL, or the posedge construct in Verilog, then you don't want to use a logic clock.  I mean ... I suppose you could but there will be subtle differences between the timing of the logic that generates the logic clock and the signals that would transition on it and those subtle differences can wreck all kinds of havoc on a design.  The clocking wizards can create "fabric clocks" for you to transition your logic on.  These "fabric clocks" don't go down to 10Hz or below.  I'm not even sure you can get them as low as 10MHz, though I might need to check on that.

To create a "logic clock" at 10Hz or below, check out the techniques listed here.  Basically, you'll create a counter and then use the transitions of the counter to generate a clock.  This can then be placed on an output pin and observed at the desired frequency.  You ... just don't want to transition on it within your design.  Since it will be generated by logic, it won't be using the clock routing resources of your design, so you'll end up with it transitioning at one time in one part of your design and nanoseconds later at another part and the two might not be consistent as you would imagine.

Dan

[MsDh]

On 5/27/2020 at 7:56 PM, D@n said:

@MsDh,

I think we need to be careful with terms.  There are two separate things that can be called a "clock".

• One is a logic signal, generated by your core, that toggles at the rate you have listed.  To create such a clock at 10Hz you don't normally need to use any of the clocking wizards you just need a counter.  I'm going to call this a "logic clock".
• This is very different from a fabric clock which you can transition your signals on.  If you want to trigger logic using the rising_edge construct in VHDL, or the posedge construct in Verilog, then you don't want to use a logic clock.  I mean ... I suppose you could but there will be subtle differences between the timing of the logic that generates the logic clock and the signals that would transition on it and those subtle differences can wreck all kinds of havoc on a design.  The clocking wizards can create "fabric clocks" for you to transition your logic on.  These "fabric clocks" don't go down to 10Hz or below.  I'm not even sure you can get them as low as 10MHz, though I might need to check on that.

To create a "logic clock" at 10Hz or below, check out the techniques listed here.  Basically, you'll create a counter and then use the transitions of the counter to generate a clock.  This can then be placed on an output pin and observed at the desired frequency.  You ... just don't want to transition on it within your design.  Since it will be generated by logic, it won't be using the clock routing resources of your design, so you'll end up with it transitioning at one time in one part of your design and nanoseconds later at another part and the two might not be consistent as you would imagine.

Dan

Hi Dan,

Thanks for your respond. I studied the article you linked here. Now I have a new question. It says "will have divided your clock by whatever value you set THRESHOLD to be." Does it mean that if I want to get 10Hz in output then I need to divide my system clock (100MHz) by 10M? The THRESHOLD's value will be 10,000,000?
Please clarify.

Thank you

 

[D@n]

@MsDh,

Sounds good.  Try it.  Tell me what happens.

Measure the clock period and its duty cycle.  Let me know if they are correct.

Dan

[MsDh]

On 5/29/2020 at 3:41 AM, D@n said:

@MsDh,

Sounds good.  Try it.  Tell me what happens.

Measure the clock period and its duty cycle.  Let me know if they are correct.

Dan

Hi Dan,

I used parts of the codes in the page you recommended me to study. Here is a module that I came up with:
module var_clk (input clk_in, reset, output clk_out);
    parameter N=26;    parameter THRESHOLD = 24'h4C4B40;
    reg new_clk;
    reg    [(N-1):0]    counter;
    always @(posedge clk_in or posedge reset)
    if (reset)
    begin
        counter<=0;
        new_clk<=0;
    end
    else
    begin
        counter <= counter + 1'b1;
        if (counter == THRESHOLD-1'b1)
        new_clk<=~new_clk;
    end
assign clk_out=new_clk;
endmodule

Assume my input signal clk_in is 100 MHz. Every time the counter reaches 5000000 then my new_clk complements. This way I set my new_clk period to 10 Hz.
Is this a good approach?
THRESHOLD defined as parameter=24'd5000000 (24'h4C4B40).
How does " (counter == THRESHOLD-1'b1)" work? When we say THRESHOLD-1'b1 means what? Means MSB of a 24-bit register or what?
Could you please explain it for me?

Thank you

 

 

 

[D@n]

@MsDh,

You are making some nice progress!  Have you tried this on your board?  How about in simulation?

2 hours ago, MsDh said:

How does " (counter == THRESHOLD-1'b1)" work? When we say THRESHOLD-1'b1 means what? Means MSB of a 24-bit register or what?

Could you please explain it for me?

Thank you

So, let me ask you, when you count up to 50M, are you counting zero or not?

Dan

[MsDh]

23 hours ago, D@n said:

@MsDh,

You are making some nice progress!  Have you tried this on your board?  How about in simulation?

So, let me ask you, when you count up to 50M, are you counting zero or not?

Dan

I think that part was a typo or mistake when pasting my code here.
One assignment must be added as you can see here in bold.
This is my modified version:
begin
        counter <= counter + 1'b1;
        if (counter == THRESHOLD-1'b1)
        counter <=0;
        new_clk<=~new_clk;
    end