mig_7series_axi4 system reset polarity

[Raghav]

Hi,

in mig.prj , I see system reset configuration as ACTIVE _LOW. But in generated verilog stub, I see below reset signals, which appears to be ACTIVE_HIGH.

Can you please clarify?

 

  input aresetn; //ACTIVE _LOW for user interface

 input sys_rst; //ACITVE_HIGH For system reset input.

 

Thanks,

Raghav

 

[elodg]

I see from your posts that you are using Genesys 2. This has a Kintex-7 FPGA, so you are talking about 7-series MIG. This is a Xilinx IP and its documentation is here: https://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v4_2/ug586_7Series_MIS.pdf.

Quote

System Reset Polarity – The polarity for system reset (sys_rst) can be selected. If the
option is selected as active-Low, the parameter RST_ACT_LOW is set to 1 and if set to
active-High the parameter RST_ACT_LOW is set to 0.

The parameter RST_ACT_LOW must control the polarity internal to the module, no matter what the comment says. If you dive into the hierarchy you should see the conditional logic.