DDR3 Interface Pin Mapping File/XDC for Digilent Genesys2 Kintex7 FPGA

[Raghav]

Hi,

The below link suggested to used fixed pin-out for DDR3 interface mapping to FPGA pins which is already provided on Digilent website. 

I used the option of letting tool do the mapping and it seems not working on FPGA. Can someone please share XDC file for AXI based MIG_7series for genesys2 Kintex7

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https://forum.digilentinc.com/topic/4035-genesys-2-board/

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The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core. For your convenience an importable UCF/XDC file is provided on the Digilent website to speed up the process.

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thank you in advance,

[Ana-Maria Balas]

Hello @Raghav,

Did you install the Digilent vivado-boards? https://reference.digilentinc.com/reference/software/vivado/board-files?redirect=1

After you install vivado-boards, when you create a project in Vivado, in the beginning  of creating the project you have to select the FPGA part or you can select the board. When you select the board all the required files related to that board are loaded. Among these files there is mig.prj file which contains the configuration for the MIG IP corresponding to the board, with the pin-out of the memory. This way you don't have to manually configure the MIG IP with the instructions from the reference manual.

You can look at the github location of the Genesys 2 from the vivado-boards to see the files: https://github.com/Digilent/vivado-boards/tree/master/new/board_files/genesys2/H

However if you need the ucf file directly: Genesys2_H.ucf

[Raghav]

Hi Ana-Maria,

Thanks.

I don't want load entire board files. Because it is already part of baseline project which was implemented for genesys2.

My requirement is to generate AXI4 based MIG and integrate with some other custom block in verilog. I followed below steps from the files you suggested to pick.

(1) Downloaded mig.prg  from https://github.com/Digilent/vivado-boards/tree/master/new/board_files/genesys2/H

(2) Downloaded Genesys2_H.ucf (that you attached above)

(3) Vivado in gui -> IP catalogue- > Customize IP -> Loaded mig.prj and Genesys2_H.ucf -> Pin selection validate.

Then FACED BELOW ERROR.

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ERROR : Location Constraint(s) is(are) not provided for certain ports even though they are required for the selected configuration. Following are the ports missing in the provided Constraints file.
"ddr3_addr[14]"

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I could notice "ddr_a" insted of "ddr_addr". I will edit *.ucf manually and proceed. Basically mismatches between mig.prj and ucf provided. .!!!

 

Thanks,

Raghav

 

 

[Ana-Maria Balas]

Yes, there are mismatches between mig.prj and ucf because were generated separately in different periods of time and was used a different name for the address. Thank you for the notice!