Nexys 4 DDR frequency synthesizer

[Islam]

Construction of a frequency synthesizer based on digital phase shifters on a DL-NEXYS4-DDR board type of Artix-7 FPGA.

Please help me make a project on Vivado 2018 using the VHDL language. I understood how the project should work, but I can’t implement it on the board.

[xc6lx45]

is this a homework problem?

[Islam]

No, I think that due to lack of knowledge. But I realized that for the implementation of this project these elements are masculine for me:
oscillator stabilized by a quartz reference signal frequency,
digital phase-frequency detector,
low pass filter
voltage controlled generator
reference frequency divider.
All these elements are Clocking Wizard, in the PLL primitive.

[xc6lx45]

OK I think there's quite a bit lost in translation.

Yes, PLL (/MMCM) are the conventional way to go, via the clocking wizard.

[Islam]

I understood first I need to build a block diagram then, something like that:

but how do I write code for simulations?

[zygot]

2 hours ago, Islam said:

I understood first I need to build a block diagram then, something like that:

In your original post you mentioned that you want to execute a VHDL project. I heartily endorse this as opposed to a board design flow.

Please read the Xilinx documentation for design flows using Vivado; UG888 and UG892 are good places to start. Doing a board design is not usually necessary unless you are targetting a ZYNQ device or have to use a MicroBlaze soft processor. You can create an HDL project without any source files. Make sure that you are selecting the correct device. The easy way to do this is to use the Digilent board files that have been added to your Vivado installation and select your board. The first thing that you want to do is change the default HDL settings from Verilog to VHDL so that your Xilinx IP wizards generate the correct output products.

Once you have a project you can browse through the Xilinx IP catalog and select the clocking wizard. Please read the Xilinx documentation for using the clocking IP available through the Xilinx Document Navigator. Don't bother to create a board design. When you've gone through the steps in the wizard you will be asked to generate output products. Do that. You can find a .vho (.veo for Verilog) file in the project directory structure under 'projectname.srcs/sources/ip/clk_wiz_0' assuming that you didn't change the default name. This file provides a text template for declaring and instantiating your clocking IP in your code. Make sure that you project has a constraints file letting Vivado know the pin locations for your toplevel port input and output signals.

Now for the fun part. You need to create a toplevel file, instantiate the clock IP, connect the output clock to some logic that drives an output pin either directly or indirectly. A simple way of seeing if you have a clock in your hardware is to connect your derived clock to a 32-bit counter that never stops counting and drive one of the LEDs with a counter bit. If your clock is 100 MHz counter(26) is a good choice. If you switch the LED on/off too quickly it won't work out as a visual indicator very well.

Hint: Most Xilinx IP can produce output products with AXI interfaces or 'native' interfaces. For HDL projects you almost always want the native interface.

[Islam]

I want to thank everyone for the answer, but the fact is that I am a student and I was given this project as a diploma project, and I need to submit it before the end of this day, I ask you for help to complete this project.
if this can be done through PLL / MMSM then how?
I am doing this project through MMSM but straight lines come out during simulations.

ЦФЧД- phese detector,

ФНЧ- Low pass filter,

ГУН- VC0. I need to do something similar to this logic

[xc6lx45]

I can only speak for myself but I'm wondering whether openly asking other people to do your homework problem is accepted use of this forum.

[D@n]

@xc6lx45,

We've always helped students on this forum.  @Islam is a long way from us doing his homework for him.

@Islam,

An FPGA is a digital device.  While it has analog components within it, such as PLLs or MMCMs, these are things you can configure--not necessarily things you can rebuild.  Indeed, most FPGA designs are digital, not analog.  Very few pay attention to phase-frequency detection, since that's normally done in the analog domain.

So let's back up and start at the top.  You will need a system clock to work with.  Your board comes with an oscillator feeding the FPGA.  Check the schematics of your board and the reference manual for details on this (crystal) oscillator.  You can use this as your system clock, or you can use a PLL or MMCM to adjust the frequency of that clock.  This frequency adjustment comes with bounds and limits on it.  You can't go too fast, and you can't go too slow.  Still, it's usually "good enough" for most FPGA work.  While it is possible to do some crazy stuff to get clocks that work outside of these bounds (but only slower), it's rarely required because you can always divide your logic (not really your clock) down to the speed you need it to be at.

Once you have a system clock to work with, you can then talk about building things using it..  Here, for example, is a discussion of how to build a phase locked loop using digital (not analog) logic.  If you wanted to build something similar using a phase frequency detector and all your loop constructs out of digital logic, you might find it to be a valuable example to examine.

FPGA design is constrained by time and how much logic can fit within one clock period.  If your PLL takes too long to calculate, you might need either 1) a faster system clock speed, or 2) a slower incoming signal.  These are design choices you will need to make, and they depend upon the application you are trying to work with.

To me, however, when you asked about a "frequency synthesizer" I wasn't thinking of raw clock generation, I thought you were interested in generating a tone of some type.  For that, you would need a Numerically Controlled Oscillator.  Those are fairly easy to build on an FPGA, and rarely require playing with the system clock speed.  Indeed, I think it's a good beginner exercise to learn how to build one of these.  There's certainly a lot to be learned in the process.

Beware, however, FPGA design looks quite easy on its face.  Most designs are built out of simple counters, shift registers, lookup tables, and finite state machines.  All those simple circuits, however, add up to some very challenging design complexity in an environment that can be quite difficult to debug.  Indeed, I might argue that learning to debug an FPGA design is more than half the challenge of designing in the first place.  Don't underestimate this task.  It's not unheard of to be stuck on an issue for weeks or even months, even though the design components are really just that easy.

Hope that helps get you started,

Dan

[zygot]

27 minutes ago, D@n said:

We've always helped students on this forum

True, but not by taking tests by proxy, nor for the purpose of helping bad students outperform hard working students on tests. I think that @D@nmissed that part about having the need for an answer before day's end. I suspect that there are a few instructors savvy enough to read posts on this forum.

[D@n]

@zygot,

I have three kids in college these days.   Every project they submit gets compared electronically against a set of known online sources before the instructor issues a grade.  Judging by the profile of my blog and the size of its readership, I'd be shocked if it wasn't on such an automatic checking list.  Neither have I solved his problem for him.  He asked for VHDL, I provided Verilog.  Worse, I provided Verilog with Verilator based test benches at that.  He asked for one form of PLL, I provided another of a similar form.  He asked for an answer, I provided reading material.  This is no more than I would do for a student who's assignment was due months from now.  Indeed, this is much of what I would expect from a student: ask a librarian for help finding relevant literature, read through that literature to find what is (or isn't) useful, and then create a project resulting from that.

I still expect that it would take a miracle for him to complete an assignment like this by days end--and the day's been wasting away for some time now, but I'm willing to pray for God's grace to take hold in his life in whatever form God might wish to offer it.

Dan

[zygot]

1 minute ago, D@n said:

I still expect that it would take a miracle for him to complete an assignment like this by days end

I suspect that there are more assumptions related to that statement, and subsequent motivation for providing a particular answer than you've consideredt. You may well have accomplished the opposite of what you intended. Nevertheless, my intention is not to criticize anyone, including the person posting the question. The topic is worthy of discourse however, if for no other reason than to make everyone stop and ponder questions outside the immediate scope of a particular technical question.