Jtag-hs3 programming issues

[JoeJosh]

I used Jtag-hs3 for some time, it worked perfectly. However, from two days, I get "ERROR: [Labtools 27-3165] End of startup status: LOW" message while I tried to program the device. I tried to change the fpga and still get this error. When I tried different computers, some can program and some get this same error. However, I tried  Xilinx platform cable II, there is no error on all FPGA's and all computers. Also, I tried different Jtag-hs3's the error is still same. What might be the problem?

 

Edit: I also tried to decrease the jtag frequency it didn't work.

[JColvin]

Hi @JoeJosh,

That particular error is usually indicative of a drop in power on the voltage supply line as per this Xilinx thread: https://forums.xilinx.com/t5/FPGA-Configuration/Error-Labtools-27-3165-End-of-startup-status-LOW/td-p/737029.

I do have some additional questions for you though.

- Have you tried using a different USB cable with the JTAG HS3? I imagine this might be the case since you mentioned testing multiple JTAG HS3's, but I figured I would check.
- Do you still encounter this issue if you use a different bitstream? And did the hardware design used change at all when this problem started occurring?
- Are you connected to a FPGA or a Zynq?
- Could you provide the output of the Config_Status registers from the Vivado Hardware Manager this can be done by running the following tcl script:

report_property [current_hw_device] -regexp REGISTER.CONFIG_STATUS.*

Thanks,
JColvin