Arty A7-100T DDR3-SDRAM Write Errors

[kringg]

I'm at a complete loss trying to get the Arty A7-100t onboard DDR-SDRAM to behave reliably. Let me start by telling you what I've done (maybe some of this will be helpful for others):

• The Arty A7-100t is running totally unmodified (no PMOD, ChipKit, etc.).
• I've generated a Memory Interface Generator (MIG) IP core as per Digilent's recommendations:
  • Digilent MIG Resources
  • My XCI and PRJ files: ddr_sdram_mig.xci and ddr_sdram_mig.prj
• I've written a simple DDR SDRAM Interface module, based on the approach found on Numato.
  • Unlike the reference code, my Verilog reads incoming addresses and reads / writes to RAM (or at least it should): ddr-sdram-interface.v
• I continually read from the aforementioned memory interface via the following code:

always @(posedge clk_100mhz) begin
  if (readReady) begin
    readAddr <= readAddr + 1;
  end
end
assign led = readData[7:0];

• I write to the memory (first all zeros, then all ones, then the address) via the following code:

always @(posedge clk_100mhz) begin
  if (writeReady) begin
    writeAddr <= writeAddr + 1;
    if ((writeAddr == 0) && (writeCounter < 3)) begin
      writeCounter <= writeCounter + 1;
    end
    case (writeCounter)
      0: writeData <= 32'h00000000;
      1: writeData <= 32'h11111111;
      2: writeData <= {8'h00, writeAddr};
      3: writeEn <= 0;
    endcase
  end
end 

Now for the problem: If I run the Verilog above exactly as-is, the LEDs show total garbage (randomness). If, instead, I continually write (the same) data to memory over-and-over again, eventually the LEDs will start flashing the binary counter I expect. This tells me that the read mechanism is functional, but the write is extremely unreliable. Any insight would be most appreciated. I purchased the Arty A7-100t in part because it has the DDR3 memory. I understand that there are significant performance issues (due to the -1 speed grade of the Artix-7 chip), but I expect to be able to attain reliable read / write behavior at low-speed.

[D@n]

@kringg,

Two insights: 1) Your resetn signal should be registered.  A combinatorial input there might cause the MIG to reset when you aren't expecting it.  2) To avoid crossing clock domains, your user interface signals (write/read address, data, etc.) should all be in the ui_clk domain and not the clk100 domain.

Dan

[TommyK]

Have you tried simulating your design? You can download the MT41K128M16JT-125 verilog memory model from Micron's website under simulation models (direct link). Place the model files into your sim sources and connect the DDR pins in the top level of your test bench code to the ddr module included in the memory model files. This will make debugging much faster for you.

 

-Tommy

[kringg]

@D@n,

Your suggestion of examining my clock domain crossings was spot-on. Thank you! There was a bug in the FIFO queue I was using to cross from system-clock-space to sdram-clock-space. Once I fixed that, everything fell into place. I'll post the final working code in a bit; I found this to be a very challenge problem due to lack of good MIG User Interface examples, so hopefully my heartburn can help someone else.

@tom21091,

Thanks for the simulation model, that'll be extremely helpful as I now integrate this subsystem into my larger project!

[kringg]

For anyone else out there who's struggling with DDR3 SDRAM on the Arty A7, here's a project for Vivado 2019.2 that builds out-of-box and successfully reads / writes (via the MIG user interface) to / from memory. Hopefully this'll save someone the pain I went through figuring out how to interface with the DDR-SDRAM via Verilog.

Arty-SDRAM.zip